Systems and methods for hardware arbitration of a communications bus

Patent metadata

Field	Value
Publication number	US-9984016-B2
Application number	US-201614989552-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jan 6, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

In accordance with embodiments of the present disclosure, an information handling system may include a communications bus, at least one target device communicatively coupled to the communications bus, and a plurality of master devices communicatively coupled to the communications bus and communicatively coupled to one another via a secondary arbitration connection. Each of the plurality of master devices may be configured to assert a respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate ownership of the communications bus and deassert the respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate non-ownership of the communications bus.

First claim

What is claimed is:

1. An information handling system comprising:
a communications bus;
at least one target device communicatively coupled to the communications bus;
a plurality of master devices communicatively coupled to the communications bus and communicatively coupled to one another via a secondary arbitration connection, wherein each of the plurality of master devices is configured to:
assert a respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate ownership of the communications bus;
deassert the respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate non-ownership of the communications bus;
participate in a standard arbitration procedure on the communications bus;
determine if another master device has asserted ownership of the communications bus by asserting the secondary arbitration signal of the other master device on the secondary arbitration connection; and
maintain assertion of its respective secondary arbitration signal and perform input/output transactions with the at least one target device via the communications bus responsive to winning the standard arbitration procedure and determining that another master device has not asserted ownership of the communications bus.

2. The information handling system of claim 1 , wherein the communications bus comprises an Inter-Integrated Circuit bus.

3. The information handling system of claim 1 , wherein the at least one target device comprises at least one of a sensor, a memory, and a power supply.

4. The information handling system of claim 1 , wherein the at least one target device comprises a device having a maximum page size for input/output operations to the device.

5. The information handling system of claim 1 , wherein the secondary arbitration connection comprises a connection between respective general purpose input/output pins of each of the plurality of master devices.

6. The information handling system of claim 1 , wherein each master device is configured to deassert its respective secondary arbitration signal responsive to losing the standard arbitration procedure.

7. The information handling system of claim 1 , wherein the at least one target device may comprise one of the plurality of master devices.

8. A method comprising, in a master device of a plurality of master devices communicatively coupled to at least one target device via a communications bus:
asserting a respective secondary arbitration signal of the master device on a secondary arbitration connection isolated from the communications bus to indicate ownership of the communications bus;
deasserting the respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate non-ownership of the communications bus;
participating in a standard arbitration procedure on the communications bus;
determining if another master device has asserted ownership of the communications bus by asserting the secondary arbitration signal of the other master device on the secondary arbitration connection; and
maintaining assertion of its respective secondary arbitration signal and performing input/output transactions with the at least one target device via the communications bus responsive to winning the standard arbitration procedure and determining that another master device has not asserted ownership of the communications bus.

9. The method of claim 8 , wherein the communications bus comprises an Inter-Integrated Circuit bus.

10. The method of claim 8 , wherein the at least one target device comprises at least one of a sensor, a memory, and a power supply.

11. The method of claim 8 , wherein the at least one target device comprises a device having a maximum page size for input/output operations to the device.

12. The method of claim 8 , wherein the secondary arbitration connection comprises a connection between respective general purpose input/output pins of each of the plurality of master devices.

13. The method of claim 8 , further comprising, in the master device, deasserting its respective secondary arbitration signal responsive to losing the standard arbitration procedure.

14. The method of claim 8 , wherein the at least one target device may comprise one of the plurality of master devices.

15. An article of manufacture comprising:
a non-transitory computer-readable medium; and
computer-executable instructions carried on the computer-readable medium, the instructions readable by a processor, the instructions, when read and executed, for causing the processor to, in a master device of a plurality of master devices communicatively coupled to at least one target device via a communications bus:
assert a respective secondary arbitration signal of the master device on a secondary arbitration connection isolated from the communications bus to indicate ownership of the communications bus; and
deassert the respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate non-ownership of the communications bus;
participate in a standard arbitration procedure on the communications bus;
determine if another master device has asserted ownership of the communications bus by asserting the secondary arbitration signal of the other master device on the secondary arbitration connection; and
maintain assertion of its respective secondary arbitration signal and perform input/output transactions with the at least one target device via the communications bus responsive to winning the standard arbitration procedure and determining that another master device has not asserted ownership of the communications bus.

16. The article of claim 15 , wherein the communications bus comprises an Inter-Integrated Circuit bus.

17. The article of claim 15 , wherein the at least one target device comprises at least one of a sensor, a memory, and a power supply.

18. The article of claim 15 , wherein the at least one target device comprises a device having a maximum page size for input/output operations to the device.

19. The article of claim 15 , wherein the secondary arbitration connection comprises a connection between respective general purpose input/output pins of each of the plurality of master devices.

20. The article of claim 15 , the instructions for further causing the processor to, in the master device, deassert its respective secondary arbitration signal responsive to losing the standard arbitration procedure.

21. The article of claim 15 , wherein the at least one target device may comprise one of the plurality of master devices.

Assignees

• Dell Products Lp

Inventors

• Yates Douglas A
• Terry Jared

Classifications

• H04L12/403

  with centralised control, e.g. polling · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/1652

  in a multiprocessor architecture (interprocessor communication using common memory G06F15/167) · CPC title