Detecting degraded core performance in multicore processors

Patent metadata

Field	Value
Publication number	US-9983966-B2
Application number	US-201514953491-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Nov 30, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An embodiment of a system is disclosed, including an interface configured to communicate to a device under test (DUT). The DUT may include a plurality of processor cores. The system also includes a testing apparatus configured to concurrently measure a performance of a portion of each processor core to generate a first set of test values. Each test value of the first set may correspond to a given processor core of the plurality of processor cores. The testing apparatus may also be configured to analyze the first set of test values, and reject the DUT in response to a determination that at least one test value of the first set of test values exceeds a first threshold.

First claim

What is claimed is:

1. A system, comprising:
an interface configured to communicate to a device under test (DUT), wherein the DUT includes a plurality of processor cores; and
a testing apparatus configured to:
generate input stimuli that causes the DUT to activate a particular portion of each processor core of the plurality of processor cores, wherein the input stimuli correspond to a particular set of instructions executed by each of the particular portions;
measure a rate at which each particular portion executes the particular set of instructions;
generate a first set of test values, the test values being based on a respective one of the measured rates, wherein each test value of the first set corresponds to a given processor core of the plurality of processor cores;
determine a first threshold based on a standard deviation of the first set of test values; and
reject the DUT in response to a determination that the DUT is defective based on at least one test value of the first set of test values being less than the first threshold.

2. The system of claim 1 , wherein each processor core of the plurality of processor cores includes a plurality of execution circuits, and wherein the particular portion of each processor core includes a respective execution circuit of the plurality of execution circuits.

3. The system of claim 2 , wherein to concurrently measure the rate at which each particular portion of each processor core executes the particular set of instructions, the testing apparatus is further configured to concurrently measure a rate at which each of at least two execution circuits in a given processor core execute the particular set of instructions.

4. The system of claim 1 , wherein the testing apparatus is further configured to:
measure a temperature corresponding to the particular portion of each processor core to generate a second set of test values;
determine a second threshold based on a standard deviation of the second set of test values; and
reject the DUT in response to a determination that the DUT is defective based on at least one test value of the second set of test values is greater than the second threshold.

5. The system of claim 1 , wherein to determine the first threshold, the testing apparatus is further configured to add a multiple of the standard deviation to a mean value.

6. The system of claim 4 , wherein the testing apparatus is further configured to compare each test value of the second set of test values to a corresponding test value of the first set of test values.

7. The system of claim 1 , wherein to measure the rate at which each particular each processor core the articular set of instructions, the testing apparatus is further configured to activate a different portion of at least one processor core of the plurality of processor cores.

8. A method comprising:
generating input stimuli that causes a processor to activate a particular portion of each core of a plurality of cores included in the processor, wherein the input stimuli correspond to a particular set of instructions executed by each of the particular portions;
measuring a rate at which each particular portion executes the particular set of instructions;
generating a first set of test values, the test values being based on a respective one of the measured rates, wherein each test value of the first set of test values corresponds to a given core of the plurality of cores;
determining a first threshold based on a standard deviation value of the first set of test values; and
rejecting the processor in response to a determination that the processor is defective based on at least one test value being less than the first threshold.

9. The method of claim 8 , wherein each core of the plurality of cores includes a plurality of execution circuits, and wherein the particular portion of each core includes a respective execution circuit of the plurality of execution circuits.

10. The method of claim 9 , wherein concurrently measuring the rate at which each particular portion of each core executes the particular set of instructions comprises concurrently measuring a rate at which each of at least two execution circuits in a respective core execute the particular set of instructions.

11. The method of claim 8 , further comprising:
measuring a temperature corresponding to the particular portion of each core to generate a second set of test values;
determining a second threshold based on a standard deviation of the second set of test values; and
rejecting the processor in response to a determination that the processor is defective based on at least one test value of the second set of test values is greater than the second threshold.

12. The method of claim 8 , further comprising:
measuring a frequency of a clock signal corresponding to the particular portion of each core to generate a second set of test values;
determining a second threshold based on a standard deviation of the second set of test values; and
rejecting the processor in response to a determination that the processor is defective based on at least one test value of the second set of test values is greater than the second threshold.

13. The method of claim 8 , further comprising determining the first threshold by adding a mean value to a multiple of the standard deviation value.

14. The method of claim 8 , wherein concurrently measuring the rate at which each particular portion of each processor core executes the particular set of instructions comprises activating a different portion of at least one processor core of the plurality of cores.

15. A non-transitory, computer accessible storage medium having program instructions stored therein that, in response to execution by a computer system, causes the computer system to perform operations comprising:
generating input stimuli that causes a processor to activate a particular portion of each core of a plurality of cores included in the processor, wherein the input stimuli correspond to a particular set of instructions executed by each of the particular portions;
measuring a rate at which each particular portion executes the particular set of instructions;
generating a first set of test values, the test values being based on a respective one of the measured rates, wherein each test value of the first set corresponds to a given core of the plurality of cores;
determining a first threshold based on a standard deviation of the first set of test values; and
rejecting the processor in response to a determination that the processor is defective based on at least one test value being less than the first threshold.

16. The non-transitory, computer accessible storage medium of claim 15 , further comprising sequentially measuring a temperature corresponding to the particular portion of each core to generate a second set of test values.

17. The non-transitory, computer accessible storage medium of claim 16 , further comprising comparing each test value of the second set of test values to a corresponding test value of the first set of test values.

18. The non-transitory, computer accessible storage medium of claim 17 , further comprising rejecting the processor in response to a determination that at least one test value of the second set of test values differs from the corresponding test value of the first set of test values by an amount greater than a second threshold.

19. The non-transitory, computer accessible storage medium of claim 15 , wherein concurrently measuring the rate at which each particular portion of each processor co

Assignees

• Oracle Int Corp

Inventors

• Parikh Alok

Classifications

• G06F11/24 Primary

  Marginal checking {or other specified testing methods not covered by G06F11/26, e.g. race tests} · CPC title

• G06F11/2242

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title