Dynamic cache sharing based on power state

Patent metadata

Field	Value
Publication number	US-9983792-B2
Application number	US-201615066111-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Aug 13, 2009
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

The present invention discloses a method comprising: sending cache request; monitoring power state; comparing said power state; allocating cache resources; filling cache; updating said power state; repeating said sending, said monitoring, said comparing, said allocating, said filling, and said updating until workload is completed.

First claim

What is claimed is:

1. A system on chip (SoC) comprising:
a first compute engine comprising a central processing unit;
a second compute engine comprising a graphics processing unit;
a cache coupled to the first compute engine and the second compute engine;
cache allocation logic associated with a way mask coupled to the cache and the first compute engine and the second compute engine, the way mask partitioned into ways, wherein some ways are dedicated to only one of the first compute engine and the second compute engine and other ways are shared between the first compute engine and the second compute engine; and
a power control unit to monitor a power state of the first compute engine and the second compute engine and to update the way mask based on the power state of the first compute engine and the second compute engine.

2. The SoC of claim 1 , further comprising a central controller coupled to the way mask.

3. The SoC of claim 2 , wherein the central controller is disposed in the power control unit.

4. The SoC of claim 2 , wherein the central controller is to monitor the power state of the first compute engine and the second compute engine, compare the power state, and allocate the cache based on the comparison.

5. The SoC of claim 4 , wherein the central controller is to monitor the power state of the first compute engine and the second compute engine concurrently.

6. The SoC of claim 4 , wherein the way mask is partitioned into ways depending on the power state of the first compute engine and the second compute engine.

7. The SoC of claim 2 , where the central controller is to monitor the power state at a first interval.

8. The SoC of claim 1 , wherein the first compute engine comprises a plurality of cores.

9. The SoC of claim 1 , wherein the cache allocation logic is to dynamically allocate the cache based at least in part on a first workload of the first compute engine and a second workload of the second compute engine.

10. The SoC of claim 1 , wherein the cache allocation logic is to dynamically allocate the cache using a prediction of cache demand.

11. The SoC of claim 1 , further comprising a single die including the first compute engine and the second compute engine.

12. The SoC of claim 1 , wherein the cache comprises a plurality of ways, at least some of the plurality of ways to be turned off to reduce power consumption.

13. The SoC of claim 1 , wherein the cache allocation logic is to adjust a cache allocation based on at least one of fuzzy logic and artificial intelligence learning.

14. A method comprising:
sending a cache request;
monitoring a power state of a first compute engine and a power state of a second compute engine;
comparing the power state of the first compute engine and the power state of the second compute engine;
allocating cache resources of a cache, comprising updating a way mask having a plurality of ways;
filling the cache;
updating the power state of the first compute engine and the power state of the second compute engine; and
repeating the sending, the monitoring, the comparing, the allocating, the filling, and the updating until a workload is completed.

15. The method of claim 14 , wherein the repeating comprises a self-regulating feedback loop.

16. An apparatus comprising:
a single die including a central processing unit (CPU) and a graphics processing unit (GPU), the single die further including a shared cache memory coupled to the CPU and the GPU, cache allocation logic associated with a way mask partitioned into a plurality of ways, wherein at least two of the plurality of ways are dedicated to the CPU and at least one of the plurality of ways is dedicated to the GPU and other ways of the plurality of ways are to be dynamically shared between the CPU and the GPU, and a power control unit to monitor a power state of the CPU and the GPU and to update the way mask based on the power state of the CPU and the GPU.

17. The apparatus of claim 16 , wherein the apparatus is to dynamically allocate the cache using a prediction of cache demand, wherein the prediction is based on a frequency of the CPU.

18. The apparatus of claim 16 , wherein the power state of the CPU is to be monitored based on information regarding a P-state and a C-state.

Assignees

• Intel Corp

Inventors

• Wells Ryan D
• Muchnick Michael J
• Ballapuram Chinnakrishnan S

Classifications

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F2212/604

  Details relating to cache allocation · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title