Dynamic cache sharing based on power state

Patent metadata

Field	Value
Publication number	US-9311245-B2
Application number	US-58303609-A
Country	US
Kind code	B2
Filing date	Aug 13, 2009
Priority date	Aug 13, 2009
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

In one embodiment, the present invention includes a cache, compute engines connected to the cache, and a way mask disposed between the cache and the compute engines. This way mask may be partitioned into ways. Some of the ways may be dedicated to only one of the compute engines and other ways can be shared among more than one of the compute engines. Other embodiments are described and claimed.

First claim

We claim:

1. A system comprising:
a cache;
compute engines connected to said cache;
cache allocation logic associated with a way mask disposed between said cache and said compute engines, said way mask partitioned into ways, wherein some ways are dedicated to only one of said compute engines and other ways are shared among more than one of said compute engines;
a power control unit to monitor a power state of said compute engines and to update said way mask based on said power state of said compute engines.

2. The system of claim 1 further comprising:
a central controller connected to said way mask.

3. The system of claim 2 wherein said central controller is disposed in said power control unit.

4. The system of claim 3 wherein said central controller is to monitor said power state of said compute engines, compare said power state, and allocate said cache.

5. The system of claim 4 wherein said way mask is partitioned into ways depending on said power state of said compute engines.

6. The system of claim 1 wherein said compute engines comprise a central processing unit.

7. The system of claim 1 wherein said compute engines comprise a graphics processing unit.

8. The system of claim 1 , wherein said system is to dynamically allocate said cache using a prediction of cache demand.

9. The system of claim 8 , wherein said prediction is based on a frequency of at least one of said compute engines.

10. The system of claim 1 , wherein said power state is monitored based on information regarding a P-state and a C-state from said compute engines.

11. An apparatus comprising:
a single die including a central processing unit (CPU) and a graphics processing unit (GPU), the single die further including a shared cache memory coupled to the CPU and the GPU, cache allocation logic associated with a way mask disposed between the shared cache memory and the CPU and the GPU, the way mask partitioned into ways, wherein some ways are dedicated to only one of the CPU and the GPU and other ways are shared among more than one of the CPU and the GPU, and a power control unit to monitor a power state of the CPU and the GPU and to update the way mask based on the power state of the CPU and the GPU.

12. The apparatus of claim 11 , wherein the apparatus is to dynamically allocate the cache using a prediction of cache demand.

13. The apparatus of claim 12 , wherein the prediction is based on a frequency of the CPU.

14. The apparatus of claim 11 , wherein the power state is monitored based on information regarding a P-state and a C-state from the CPU.

15. The apparatus of claim 11 , wherein the cache allocation logic is to adjust a cache allocation based on fuzzy logic.

16. The apparatus of claim 11 , wherein the cache allocation logic is to adjust a cache allocation based on artificial intelligence learning.

17. A system comprising:
a single die including a central processing unit (CPU) and a graphics processing unit (GPU), the single die further including a shared cache memory, compute engines connected to the shared cache memory, cache allocation logic associated with a way mask disposed between the shared cache memory and the compute engines, the way mask partitioned into ways, wherein some ways are dedicated to only one of the compute engines and other ways are shared among more than one of the compute engines, and a power control unit to monitor a power state of the compute engines and to update the way mask based on the power state of the compute engines, wherein the system is to send a cache request, monitor the power state, compare the power state to a first value, allocate the shared cache memory, fill the shared cache memory, update the power state, respectively, iteratively until a workload is completed.

Assignees

• Wells Ryan D
• Muchnick Michael J
• Ballapuram Chinnakrishnan S
• Intel Corp

Inventors

• Wells Ryan D
• Muchnick Michael J
• Ballapuram Chinnakrishnan S

Classifications

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F2212/604

  Details relating to cache allocation · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F2212/6046

  Using a specific cache allocation policy other than replacement policy · CPC title