Method for detecting substrate crack, substrate, and detection circuit

Patent metadata

Field	Value
Publication number	US-9983452-B2
Application number	US-201415326308-A
Country	US
Kind code	B2
Filing date	Jul 15, 2014
Priority date	Jul 15, 2014
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A method for detecting a substrate crack, a substrate, and a detection circuit. A non-closed test line having an opening is peripherally disposed along an edge of a glass substrate of a TFT substrate. Whether an edge of the TFT substrate has a crack or chip can be determined by measuring whether the test line is on or off. In this way, a detection omission can be avoided, detection efficiency is improved, and after the TFT substrate is used to assemble a liquid crystal module or the liquid crystal module is used to assemble a complete device, whether the edge of the TFT substrate in the liquid crystal module has a crack or chip can also be detected.

First claim

What is claimed is:

1. An electronic terminal, comprising:
a liquid crystal display comprising a thin film transistor (TFT) substrate,
wherein the TFT substrate comprises a glass substrate,
wherein a non-closed test line having an opening is peripherally disposed on the glass substrate along an edge of the glass substrate,
wherein the opening is formed by two end points of the test line,
wherein one of the two end points is grounded,
wherein the opening is located in an interference fit flexible printed circuit board on glass (FOG) bonding region between a flexible printed circuit board and the glass substrate,
wherein the two end points of the opening are electrically connected to a first connector interface by using the flexible printed circuit board,
wherein the first connector interface is configured to electrically connect to a connector interface of a detection circuit, and
wherein the detection circuit is configured to measure whether the test line is on or off to determine whether an edge of the TFT substrate has a crack or chip.

2. The electronic terminal according to claim 1 , wherein a conducting layer of the test line is manufactured as any conducting layer in a TFT substrate manufacturing process, and wherein the test line is manufactured together with a conductive pattern of the conducting layer in a patterning process for the conducting layer.

3. The electronic terminal according to claim 2 , wherein the conducting layer is a gate metal layer, and wherein the conductive pattern of the conducting layer is a gate metal wire.

4. The electronic terminal according to claim 3 , wherein a distance between the test line and the edge of the glass substrate is 150 micrometers (μm) to 200 μm.

5. The electronic terminal according to claim 2 , wherein the conducting layer is a source drain metal layer, and wherein the conductive pattern of the conducting layer is a source drain metal wire.

6. The electronic terminal according to claim 5 , wherein a distance between the test line and the edge of the glass substrate is 150 micrometers (μm) to 200 μm.

7. The electronic terminal according to claim 2 , wherein the conducting layer is a transparent conducting thin film, and wherein the conductive pattern of the conducting layer is a pixel electrode.

8. The electronic terminal according to claim 7 , wherein a distance between the test line and the edge of the glass substrate is 100 micrometers (μm).

9. The electronic terminal according to claim 1 , further comprising a detection circuit, comprising:
an analog to digital converter interface;
a power supply;
a resistor;
a second connector interface; and
a test bed,
wherein the power supply is electrically connected to a first end of the resistor,
wherein a second end of the resistor is electrically connected to the second connector interface,
wherein a first end of the analog to digital converter interface is electrically connected to the second end of the resistor,
wherein a second end of the analog to digital converter interface is electrically connected to the test bed,
wherein a series circuit comprising the power supply, the resistor, and the TFT substrate is formed when a first connector interface in the TFT substrate is electrically connected to the second connector interface, and
wherein the test bed is configured to:
measure an electrical parameter at a connection point between the resistor and the second connector interface in the series circuit; and
determine whether an edge of the TFT substrate has the crack or chip according to the electrical parameter.

Assignees

• Huawei Tech Co Ltd

Inventors

• Jia Yanfeng
• Tang Lei
• Xie Pengfei

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• G02F1/13452

  Conductors connecting driver circuitry and terminals of panels · CPC title

• G02F2201/123

  pixel · CPC title

• G02F1/136259 Primary

  Repairing; Defects · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title