TFT array substrate, liquid crystal panel having the same, and method of manufacturing the TFT array substrate

US9110342B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9110342-B2
Application numberUS-201314061445-A
CountryUS
Kind codeB2
Filing dateOct 23, 2013
Priority dateNov 12, 2012
Publication dateAug 18, 2015
Grant dateAug 18, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A TFT array substrate includes: a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; a switching element, which is disposed at an intersection of the gate wiring and the source wiring; a counter electrode, which is formed on the pixel electrode with interposing an insulating film; and a silicon film is formed on a lower layer so as to face the source wiring, wherein the source wiring and the pixel electrode are formed of the same transparent conductive material layer, and the source wiring and the silicon film are formed so that end faces of the source wiring and the silicon film are overlapped and a width of the source wiring is identical to a width of the silicon film, in a plan view.

First claim

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What is claimed is: 1. A TFT array substrate employing a fringe field mode comprising: a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; a switching element, which is disposed at an intersection of the gate wiring and the source wiring; a counter electrode, which is formed on the pixel electrode with an insulating film interposed therebetween; and a silicon film formed on a lower l…

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What does patent US9110342B2 cover?
A TFT array substrate includes: a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; a switching element, which is disposed at an intersection of the gate wiring and the source wiring; a counter electrode, which is formed on the pixel electrode with interposing an insulating film; and a silicon film is f…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification G02F1/134363. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).