Integrated linear current sense circuitry for semiconductor transistor devices

Patent metadata

Field	Value
Publication number	US-9983239-B2
Application number	US-201615154702-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	May 13, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An integrated circuit (IC) for sensing a current flowing through a transistor device includes a substrate and a current scaling circuit that includes first and second MOSFET devices. The first MOSFET device has a drain coupled to the switched FET at a first node and a source coupled to the substrate. The second MOSFET device has a source coupled to the substrate and a drain coupled to a second node. The first MOSFET device has a channel size that is K times larger than the second MOSFET device. Circuitry is included that equalizes a voltage across both the first MOSFET device and the second MOSFET device.

First claim

I claim:

1. An integrated circuit (IC) for sensing a main current flowing through a transistor device, the IC comprising:
a substrate;
a current scaling circuit that includes first and second MOSFET devices, the first MOSFET device having a drain coupled to the transistor device at a first node and a source coupled to the substrate, the second MOSFET device having a source coupled to the substrate and a drain coupled to a second node, the first and second MOSFET devices each have a gate that is commonly coupled to receive a gate drive signal, the first MOSFET device having a channel size that is K times larger, where K is an integer greater than 1, as compared to the second MOSFET device, thereby producing a current ratio of K:1 between the first and second MOSFET devices in operation; and
circuitry coupled to the first and second nodes which equalizes a voltage across both the first MOSFET device and the second MOSFET device.

2. The IC of claim 1 further comprising a current mirror having a first side coupled to the second node, and a second side, a secondary current flowing through the first side and a sense current flowing through the second side of the current mirror.

3. The IC of claim 1 wherein the sources of the first and second MOSFET devices are connected directly to the substrate.

4. The IC of claim 1 wherein the circuitry comprises an equalizer circuit having a first input coupled to the first node and a second input coupled to the second node, the equalizer circuit outputting an equalizer signal in response to a voltage difference across the first and second inputs.

5. The IC of claim 4 wherein the circuitry further comprises a modulator circuit coupled to receive the equalizer signal and, responsive to the equalizer signal, modulate a secondary current flowing through the second MOSFET device to equalize the voltage across both the first MOSFET device and the second MOSFET device.

6. The IC of claim 2 wherein the first side of the current mirror includes a first PMOS transistor coupled between a voltage supply and the second node, the second side of the current mirror includes a second PMOS transistor coupled to the voltage supply, the first and second PMOS transistors each having a gate commonly coupled to the second node.

7. The IC of claim 6 wherein the first PMOS transistor has a size that is M times larger, where M is an integer greater than or equal to 1, as compared to the second PMOS transistor, thereby producing a current ratio of M:1 between the first and second PMOS transistors in operation.

8. The IC of claim 7 wherein a total ratio of the main current to the sense current is (K×M):1.

9. The IC of claim 2 wherein the current mirror further comprises one or more additional cascoded current mirror stages.

10. The IC of claim 4 wherein the equalizer circuit comprises an operational amplifier.

11. The IC of claim 5 wherein the modulator circuit comprises a second transistor device coupled to the second node.

12. The IC of claim 11 wherein the second transistor device is a MOSFET that operates in a linear mode.

13. The IC of claim 11 wherein the second transistor device is a bipolar junction transistor (BJT) that operates in a linear mode.

14. The IC of claim 12 wherein the modulator circuit further includes a resistor having one end connected to the gate of the MOSFET and another end coupled to receive the equalizing signal.

15. The IC of claim 1 wherein the transistor device comprises a gallium nitride (GaN) high electron mobility FET (HEMFET).

16. The IC of claim 1 further comprising a current sense component coupled to receive the sense current.

17. The IC of claim 4 wherein the circuitry further comprises a high-voltage blocker circuit coupled between the first node and the first input of the equalizer circuit.

18. The IC of claim 17 wherein the high-voltage blocker circuit comprises a normally-ON high voltage JFET.

19. The IC of claim 17 wherein the first and second MOSFET devices are monolithic devices having substantially the same characteristic parameters.

20. The IC of claim 7 wherein M is an integer greater than 1.

Assignees

• Power Integrations Inc

Inventors

• Mayell Robert

Classifications

• G01R19/0092 Primary

  Measuring current only · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L27/0623

  Electricity · mapped topic

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title