Power MOSFET current sense structure and method

Patent metadata

Field	Value
Publication number	US-9293535-B2
Application number	US-201213610901-A
Country	US
Kind code	B2
Filing date	Sep 12, 2012
Priority date	Jun 12, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET ( 304 ) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

First claim

What is claimed is:

1. A power metal-oxide-semiconductor-field-effect-transistor (MOSFET), comprising:
a substrate having upper and lower surfaces;
a main field effect transistor (MFET) formed in the substrate, having multiple MFET source regions and MFET gate runners extending to the upper surface, underlying an MFET source metal coupled to the multiple MFET source regions, and a drain region and a drain contact proximate the lower surface;
a current sensing field effect transistor (SFET) formed in the substrate, having multiple SFET source regions and SFET gate runners extending to the upper surface, underlying an SFET source metal coupled to the multiple SFET source regions, and a drain region and a drain contact proximate to the lower surface, wherein the SFET is laterally embedded within the MFET but separated from the MFET by a buffer region; and
isolation gate runners located in the buffer region and electrically coupling the MFET gate runners to the SFET gate runners while electrically separating the MFET source regions and the SFET source regions, wherein the isolation gate runners are connected end-to-end such that each of the isolation gate runners has at least one end directly physically connected to an end of an adjacent isolation gate runner, and adjacent isolation gate runners have one common end directly physically coupled to one of the MFET gate runners, and each of the isolation gate runners has a middle portion directly physically connected to one of the SFET gate runners.

2. The power MOSFET of claim 1 , wherein the isolation gate runners couple the SFET gate runners together and couple the MFET gate runners together, and further connect the MFET gate runners and the SFET gate runners to each other.

3. The power MOSFET of claim 2 , wherein the isolation gate runners have a zigzag like plan view layout configuration, with the SFET gate runners coupled to the zigs and the MFET gate runners coupled to the zags of the isolation gate runners.

4. The power MOSFET of claim 3 , wherein the zigzag like plan view layout configuration of the isolation gate runners have a saw-tooth like plan view layout configuration.

5. The power MOSFET of claim 1 , wherein a first set of n isolation gate runners couple a first set of n+1 MFET gate runners to first terminals of a set of n SFET gate runners and a second set of n isolation gate runners couple a second set of n+1 MFET gate runners to second terminals of the set of n SFET gate runners, where n is a number.

6. The power MOSFET of claim 5 , wherein the first and second sets of n isolation gate runners each comprises 2n+1 isolation gate runner connections.

7. The power MOSFET of claim 5 , wherein a first MFET gate runner of the first set of n+1 MFET gate runners is coupled to a first SFET gate runner of the set of n SFET gate runners by a first isolation gate runner of the first set of n isolation gate runners and wherein a (n+1) th MFET gate runner of the first set of n+1 MFET gate runners is coupled to a n th SFET gate runner of the set of n SFET gate runners by a n th isolation gate runner of the first set of n isolation gate runners.

8. The power MOSFET of claim 7 , wherein the MOSFET further comprises a first body region in which the first isolation gate runner is embedded, and further comprising a first region of higher doping concentration compared to the first body region proximate to an outboard side of the first isolation gate runner between an outboard side of the first MFET gate runner and an outboard side of the first SFET gate runner, wherein the outboard sides of the first isolation gate runner, the first MFET gate runner and the first SFET gate runner are proximate to a first side of the substrate parallel to the SFET gate runners.

9. The power MOSFET of claim 8 , wherein the first region of higher doping concentration compared to the first body region has a doping concentration exceeding that of the first body region proximate to the outboard side of the first isolation gate runner between the outboard side of the first MFET gate runner and the outboard side of the first SFET gate runner by a factor of about 20 or more.

10. The power MOSFET of claim 8 , wherein the MOSFET further comprises a second body region in which the n th isolation gate runner is embedded, and further comprising a second region of higher doping concentration compared to the second body region proximate to an outboard side of the n th isolation gate runner between an outboard side of the (n+1) th MFET gate runner and an outboard side of the n th SFET gate runner, wherein the outboard sides of the n th isolation gate runner, the (n+1) th MFET gate runner and the n th SFET gate runner are proximate to a second side opposite to the first side of the substrate.

11. The power MOSFET of claim 10 , wherein the second region of higher doping concentration compared to the second body region has a doping concentration exceeding that of the body region proximate to the outboard side of the n th isolation gate runner between the outboard side of the (n+1) th MFET gate runner and the outboard side of the n th SFET gate runner by a factor of about 20 or more.

12. A power metal-oxide-semiconductor-field-effect-transistor (MOSFET) incorporating a main-field-effect-transistor (MFET) and a current sensing-field-effect-transistor (SFET), comprising:
a substrate having upper and lower surfaces, wherein the substrate includes a body region of the power MOSFET;
multiple gate trenches extending into the body region from the upper surface, and having a first group for the MFET, a second group for the SFET and a third group coupling the first and second groups of trenches, wherein the gate trenches of the third group are connected end-to-end such that each of the gate trenches of the third group has at least has one end directly connected to an end of an adjacent gate trench of the third group, and adjacent gate trenches of the third group have one common end directly coupled to one of the gate trenches of the first group, and each of the gate trenches of the third group has a middle portion directly connected to one of the gate trenches of the second group;
dielectric liners in the multiple gate trenches;
gate conductor filling the multiple gate trenches;
first sources adjacent to the first group, and second sources adjacent to the second group, wherein doping in portions of the body region adjacent to the dielectric liners of the third group exceeds background doping of the body region; and
a first source metal coupled to the first sources and a second source metal spaced apart from the first source metal coupled to the second sources.

13. The power MOSFET of claim 12 , wherein the doping in portions of the body region adjacent to the dielectric liners of the third group exceeds the background doping of the body region by a factor of about 20 or more.

Assignees

• Wang Peilin
• Chen Jingjing
• De Fresart Edouard D
• Ku Pon Sung
• Li Wenyi
• Qin Ganming
• Freescale Semiconductor Inc

Inventors

• Wang Peilin
• Chen Jingjing
• De Fresart Edouard D
• Ku Pon Sung
• Li Wenyi
• Qin Ganming

Classifications

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/154

  Dispositions · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D30/669

  having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title