Hybrid analog and digital control of oscillator frequency

Patent metadata

Field	Value
Publication number	US-9705514-B2
Application number	US-201414554798-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Nov 27, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.

First claim

What is claimed is:

1. A phase-locked loop comprising:
a digital control path to control a first plurality of varactors within a tank circuit of an oscillator; and
an analog control path to control a second plurality of varactors within the tank circuit to control frequency of the oscillator.

2. The phase-locked loop as recited in claim 1 wherein the analog control path acts to reduce a range required of the digital control path.

3. The phase-locked loop as recited in claim 1 wherein a frequency response of the analog control path intersects a digital control path frequency response at a frequency close to or lower than a zero contained in the digital control path frequency response.

4. The phase-locked loop (PLL) as recited in claim 1 wherein a bandwidth of the analog control path is below a bandwidth of the PLL such that the analog control path has a non-dominant effect on the bandwidth and stability performance of the PLL.

5. The phase locked loop as recited in claim 1 further comprising a delta sigma modulator in the digital control path, an output of the delta sigma modulator coupled to control one or more of the first plurality of varactors.

6. The phase locked loop as recited in claim 1 wherein control signaling in the digital control path for the first plurality of varactors is binary and for the analog control path respective analog control signals for the second plurality of varactors are coupled to a first voltage, a second voltage, or a tuning voltage with a range spanning the first and second voltages.

7. The phase locked loop as recited in claim 1 wherein the analog control path has only one of the second plurality of varactors being actively tuned at a time and respective control signals for remaining ones of the second plurality of varactors are set to a first or second voltage while the one of the second plurality of varactors that is being actively tuned has its control signal set to a tuning voltage with a range spanning the first and second voltages.

8. The phase locked loop as recited in claim 1 wherein the analog control path includes a delta sigma modulator coupled to a low pass filter to supply an analog varactor control signal for an active varactor.

9. The phase locked loop as recited in claim 8 wherein the delta sigma modulator is a digital second order delta sigma modulator and the low pass filter is an RC filter.

10. The phase locked loop as recited in claim 1 ,
wherein the digital control path includes a digital filter coupled to receive a phase error signal; and
wherein the analog control path includes,
a summing circuit coupled to receive a frequency error signal and coupled to receive an output of the digital control path;
an accumulator circuit coupled to accumulate an output of the summing circuit;
a delta sigma modulator coupled to the accumulator circuit; and
a low pass filter coupled to an output of the delta sigma modulator to supply an analog varactor tuning signal to control one or more of the second plurality of varactors.

11. The phase locked loop as recited in claim 10 wherein the digital filter comprises:
a feedforward path;
an accumulator path including a second accumulator circuit; and
a second summing circuit coupled to sum an output of the second accumulator circuit and an output of the feedforward path, an output of the second summing circuit being supplied to the summing circuit of the analog control path; and
wherein the digital control path includes a second delta sigma modulator coupled to receive the second summing circuit output and to control one or more of the first plurality of varactors.

12. A method of operating a phase-locked loop comprising:
controlling a first plurality of varactors within a tank circuit of an oscillator of the phased-locked loop using a digital control path; and
controlling a second plurality of varactors within the tank circuit of the oscillator using an analog control path.

13. The method as recited in claim 12 further comprising the analog control path centering the digital control path in a desired input range of the digital control path.

14. The method as recited in claim 12 further comprising operating the analog control path with a bandwidth such that the analog control path creates a zero in a phase-locked loop (PLL) transfer function that occurs at a frequency less than one third of an overall PLL bandwidth.

15. The method as recited in claim 12 further comprising controlling one or more of the first plurality of varactors with a delta sigma modulator in the digital control path.

16. The method as recited in claim 12 further comprising:
utilizing binary control signaling for the digital control path; and
coupling respective analog control signals for the second plurality of varactors to a first voltage, a second voltage, or a tuning voltage with a range spanning the first and second voltages for the analog control path.

17. The method as recited in claim 12 further comprising activating only one of the second plurality of varactors at a time by controlling the activated one of the second plurality of varactors with a tuning voltage.

18. The method as recited in claim 12 further comprising generating an analog control signal in the analog control path using a delta sigma modulator and a low pass filter to supply an analog varactor control signal to an active varactor of the second plurality of varactors.

19. The method as recited in claim 12 further comprising:
in the digital control path accumulating a phase error signal and generating an accumulator output;
summing the accumulator output and a feed forward path output to generate a first sum;
supplying the first sum to a first delta sigma modulator;
supplying an output of the first delta sigma modulator as a dithered control signal for at least one varactor of the first plurality of varactors;
in the analog control path accumulating the first sum in a second accumulator;
supplying an output of the second accumulator to a second delta sigma modulator; and
low pass filtering an output of the second delta sigma modulator to generate an analog varactor tuning signal for an active varactor.

20. A phase-locked loop comprising:
a digital control path coupled to receive a phase error signal and to control a first plurality of varactors within a tank circuit of an oscillator, the digital control path including a digital filter; and
an analog control path configured to control a second plurality of varactors within the tank circuit, the analog control path coupled to receive an output of the digital control path and to generate analog control signals for the second plurality of varactors.

Assignees

• Silicon Lab Inc

Inventors

• Perrott Michael H

Classifications

• H03L7/0991 Primary

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/0802

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• H03L7/0994

  comprising an accumulator · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title