Integrated circuit devices and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9978881-B2
Application number	US-201715598675-A
Country	US
Kind code	B2
Filing date	May 18, 2017
Priority date	Aug 5, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
first and second fin active regions formed on a substrate and extending in a first direction parallel to a top surface of the substrate;
a first gate structure disposed on a side surface of the first fin active region;
a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region;
a second gate structure disposed on a side surface of the second fin active region; and
a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region,
wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.

2. The integrated circuit device as claimed in claim 1 , wherein a second effective channel length between the pair of second impurity regions formed in the second fin active region is longer than a first effective channel length between the pair of first impurity regions formed in the first fin active region.

3. The integrated circuit device as claimed in claim 1 , wherein a horizontal cross-sectional area of the pair of second impurity regions is smaller than a horizontal cross-sectional area of the second fin active region.

4. The integrated circuit device as claimed in claim 1 , wherein a distance between the pair of second impurity regions is greater than a distance between the pair of first impurity regions.

5. The integrated circuit device as claimed in claim 1 , wherein:
the first gate structure includes a first gate electrode surrounding the side surface of the first fin active region and a first gate insulation layer between the first fin active region and the first gate electrode, and
the second gate structure includes a second gate electrode surrounding the side surface of the second fin active region and a second gate insulation layer between the second fin active region and the second gate electrode, the second gate insulation layer being thicker than the first gate insulation layer.

6. The integrated circuit device as claimed in claim 1 , wherein:
one of the pair of second impurity regions is formed in a portion of the top portion of the second fin active region, and
the other of the pair of second impurity regions is formed in a portion of the bottom portion of the second fin active region and spaced apart from the one of the pair of second impurity regions in the first direction.

7. The integrated circuit device as claimed in claim 6 , wherein:
the top portion of the second fin active region has top surfaces at different levels, and
a top surface of a portion where one of the pair of second impurity regions is disposed is at a higher level than a top surface of a portion where the one of the pair of second impurity regions is not disposed.

8. The integrated circuit device as claimed in claim 1 , wherein:
one of the pair of second impurity regions is formed in a portion of the top portion of the second fin active region, and
the other of the pair of second impurity regions is formed in a portion of the top portion of the second fin active region and spaced apart from the one of the pair of second impurity regions in the first direction.

9. The integrated circuit device as claimed in claim 1 , wherein:
one of the pair of second impurity regions is formed in a portion of the bottom portion of the second fin active region, and
the other of the pair of second impurity regions is formed in a portion of the bottom portion of the second fin active region and spaced apart from the one of the pair of second impurity regions in the first direction.

10. The integrated circuit device as claimed in claim 9 , wherein a top surface of the second fin active region is at a lower level than a top surface of the first fin active region.

11. The integrated circuit device as claimed in claim 1 , further comprising a third impurity region that is disposed in the top portion or the bottom portion of the second fin active region, wherein the third impurity region is spaced apart from one of the pair of second impurity region at a same level as the one second impurity region.

12. The integrated circuit device as claimed in claim 1 , wherein the first and second fin active regions include an epitaxial semiconductor layer on the substrate.

13. An integrated circuit device, comprising:
a substrate including first and second fin active regions;
a first transistor formed on the substrate, the first transistor including a first gate structure formed on a side surface of the first fin active region and a pair of first impurity regions formed in a top portion and a bottom portion of the first fin active region; and
a second transistor formed on the substrate, the second transistor including a second gate structure formed on a side surface of the second fin active region and having a same height as the first gate structure and a pair of second impurity regions formed in a top portion or a bottom portion of the second fin active region,
wherein an effective channel length of the second transistor is longer than an effective channel length of the first transistor.

14. The integrated circuit device as claimed in claim 13 , wherein:
the pair of first impurity regions include a first top impurity region disposed in the top portion of the first fin active region and a first bottom impurity region disposed in the bottom portion of the first fin active region and vertically overlapping the first top impurity region, and
the pair of second impurity regions include a second top impurity region disposed in a portion of the top portion of the second fin active region and a second bottom impurity region disposed in a portion of the bottom portion of the second fin active region, wherein the second bottom impurity region does not vertically overlap the second top impurity region.

15. The integrated circuit device as claimed in claim 13 , wherein the pair of second impurity regions include second and third top impurity regions spaced apart from each other in the top portion of the second fin active region or second and third bottom impurity regions spaced apart from each other in the bottom portion of the second fin active region.

16. An integrated circuit device, comprising:
first and second fin active regions formed on a substrate and extending in a first direction parallel to a top surface of the substrate;
a first gate structure disposed on a side surface of the first fin active region, an upper first impurity region disposed above the first gate structure, and a lower first impurity region disposed below the first gate structure of the first fin active region;
a second gate structure disposed on a side surface of the second fin active region, an upper second impurity region disposed above the second gate structure, and a lower second impurity region disposed below the second gate structure of the second fin active region,
wherein a distance between closest points of the upper and lower second impurity regions is greater than a distance between closest points of the upper and lower first impurity regions.

17. The integrated circuit device as claimed in claim 16 , wherein a midpoint of the second fin active region, as determined in a longitudinal direction of the second fin active region, is not overlapped by the upper second impurity region and is not overlapped by the lower second impurity region.

18. The integrated circuit device as claimed in claim 16 , wherein the first fin active region is in a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cantoro Mirco
• Heo Yeon-Cheol
• LUQUE Maria Toledano

Classifications

• H01L29/78609

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic