Flash memory cell

Patent metadata

Field	Value
Publication number	US-9978758-B1
Application number	US-201715613103-A
Country	US
Kind code	B1
Filing date	Jun 2, 2017
Priority date	May 26, 2017
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.

First claim

What is claimed is:

1. A flash memory, comprising:
a substrate;
a memory gate on the substrate;
a charge-storage layer between the memory gate and the substrate;
a select gate adjacent to the memory gate, wherein the select gate comprises an upper portion and a lower portion;
a select gate dielectric layer between the select gate and the substrate;
a first oxide-nitride spacer between the memory gate and the select gate; and

a second oxide-nitride spacer between the first oxide-nitride spacer and the upper portion of the select gate; and
a recessed region that undercuts the second oxide-nitride spacer.

2. The flash memory according to claim 1 , wherein the memory gate has a first sidewall surface and a second sidewall surface that is opposite to the first sidewall surface.

3. The flash memory according to claim 2 , wherein the select gate is disposed only on the second sidewall surface.

4. The flash memory according to claim 3 , wherein second oxide-nitride spacer is disposed only between the first oxide-nitride spacer and the upper portion of the select gate above the recessed region.

5. The flash memory according to claim 4 , wherein a first lightly-doped drain (LDD) spacer is disposed on the first sidewall surface of the memory gate, wherein a first lightly-doped drain (LDD) region is disposed in the substrate and is directly under the first LDD spacer.

6. The flash memory according to claim 5 , wherein a source doping region is disposed in the substrate and is adjacent to the first LDD region.

7. The flash memory according to claim 5 , wherein a second lightly-doped drain (LDD) spacer is disposed on the select gate, wherein a second lightly-doped drain (LDD) region is disposed in the substrate and is directly under the second LDD spacer.

8. The flash memory according to claim 7 , wherein a drain doping region is disposed in the substrate and is adjacent to the second LDD region.

9. The flash memory according to claim 1 , wherein the lower portion of the select gate extends into the recessed region.

10. The flash memory according to claim 9 , wherein the first oxide-nitride layer comprises a first silicon oxide layer and a first silicon nitride layer, and the second oxide-nitride layer comprises a second silicon oxide layer and a second silicon nitride layer, wherein the second silicon oxide layer is in direct contact with the first silicon nitride layer.

11. The flash memory according to claim 10 , wherein the first silicon oxide layer has first thickness and the second silicon oxide layer has a second thickness, wherein the second thickness is thicker than the first thickness.

12. The flash memory according to claim 11 , wherein the recessed region has a height that is equal to the second thickness.

13. The flash memory according to claim 11 , wherein the second thickness ranges between 10˜30 nm.

14. The flash memory according to claim 1 , wherein the charge-storage layer comprises an oxide-nitride-oxide (ONO) layer.

15. The flash memory according to claim 1 , wherein the memory gate comprises polysilicon.

16. The flash memory according to claim 1 , wherein the select gate comprise polysilicon.

17. The flash memory according to claim 1 , wherein the substrate comprises a silicon substrate.

Assignees

• United Microelectronics Corp

Inventors

• Liu Weichang
• Chen Zhen
• Wang Shen-De
• Xiang Wang
• Ta Wei
• Sun Chuan

Classifications

• H10P14/6927 Primary

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H01L27/11517 Primary

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic

• H01L21/283

  Electricity · mapped topic

• H01L21/0214

  Electricity · mapped topic