Semiconductor chips and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9978756-B2
Application number	US-201715412689-A
Country	US
Kind code	B2
Filing date	Jan 23, 2017
Priority date	May 16, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a peripheral circuit region on a surface of a substrate;
a semiconductor layer on the peripheral circuit region;
a layer that is electrically connected to, and extends laterally in a first direction adjacent a side of, the semiconductor layer, wherein the first direction and a second direction are perpendicular to each other and are parallel to the surface of the substrate, and wherein, in a plan view, the layer extends shorter distances in the first direction and the second direction, respectively, than the semiconductor layer; and
a cell region on the semiconductor layer.

2. The semiconductor chip of claim 1 , wherein the layer that is electrically connected to the semiconductor layer is at a same layer level as the semiconductor layer.

3. The semiconductor chip of claim 1 , wherein the semiconductor layer and the layer that is electrically connected to the semiconductor layer comprise a same material.

4. The semiconductor chip of claim 3 , wherein the semiconductor layer and the layer that is electrically connected to the semiconductor layer comprise respective polysilicon layers.

5. The semiconductor chip of claim 3 , wherein the semiconductor layer and the layer that is electrically connected to the semiconductor layer comprise respective single crystalline silicon layers.

6. The semiconductor chip of claim 1 , wherein the layer that is electrically connected to the semiconductor layer comprises a conductive layer.

7. The semiconductor chip of claim 1 , further comprising a pad region at a side of the cell region.

8. The semiconductor chip of claim 7 , wherein the pad region overlaps the layer that is electrically connected to the semiconductor layer in a third direction perpendicular to the surface of the substrate.

9. The semiconductor chip of claim 7 , wherein the pad region overlaps the semiconductor layer in a third direction perpendicular to the surface of the substrate.

10. A semiconductor chip comprising:
a peripheral circuit on a substrate;
a semiconductor layer on the peripheral circuit;
a layer at a same layer level as the semiconductor layer and electrically connected to a portion of the semiconductor layer, wherein the layer laterally protrudes from the semiconductor layer and is narrower, in a plan view, than the peripheral circuit; and
a cell region on the semiconductor layer and comprising a transistor of a memory cell.

11. The semiconductor chip of claim 10 , wherein the layer that is at the same layer level as the semiconductor layer and is electrically connected to the portion of the semiconductor layer is at a boundary region of the semiconductor layer and comprises a polysilicon layer or a single crystalline silicon layer.

12. The semiconductor chip of claim 10 , wherein the memory cell overlaps the peripheral circuit on the substrate.

13. The semiconductor chip of claim 10 , wherein the peripheral circuit comprises a page buffer, a latch circuit, a cache circuit, a row decoder, a column decoder, a sense amplifier, or a data in/out circuit.

14. The semiconductor chip of claim 10 , further comprising a peripheral circuit wiring structure in the cell region and electrically connected to the peripheral circuit.

15. A semiconductor chip comprising:
a substrate;
a memory cell region on the substrate;
a peripheral circuit region between the memory cell region and the substrate, wherein the peripheral circuit region comprises circuitry configured to process data input into and/or output from the memory cell region;
a semiconductor layer between the memory cell region and the peripheral circuit region; and
a connector that extends laterally from a perimeter portion of the semiconductor layer,
wherein an outermost portion of the connector comprises a cut portion of the semiconductor chip, and
wherein, in a plan view, the outermost portion of the connector is narrower, in a cut direction of the connector, than the semiconductor layer.

16. The semiconductor chip of claim 15 , wherein the connector comprises a conductive material or a same material as the semiconductor layer.

17. The semiconductor chip of claim 16 ,
wherein the connector comprises a first connector on a first side of the semiconductor layer, and
wherein the semiconductor chip further comprises a second connector on a second side of the semiconductor layer.

18. The semiconductor chip of claim 15 , wherein the connector defines a portion of an outermost edge of the semiconductor chip.

19. The semiconductor chip of claim 15 ,
wherein the semiconductor layer comprises a well region, and
wherein the connector is adjacent the well region of the semiconductor layer.

20. The semiconductor chip of claim 15 , wherein the cut direction of the connector comprises a first direction that is perpendicular to a second direction in which the connector extends laterally from the perimeter portion of the semiconductor layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyuk
• Chung Seung-Pil
• Min Jae-Ho

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11286 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H10B43/23

  with source and drain on different levels, e.g. with sloping channels · CPC title

• H10B41/23

  with source and drain on different levels, e.g. with sloping channels · CPC title