Method of performing static timing analysis for an integrated circuit

Patent metadata

Field	Value
Publication number	US-9977845-B2
Application number	US-201514982921-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Jan 22, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method of performing a static timing analysis on an integrated circuit includes loading a library that includes local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained based on a set of a plurality of global variation parameters of the integrated circuit, calculating delays of timing arcs included in the integrated circuit based on the library, and determining whether at least one timing path of a plurality of timing paths included in the integrated circuit violates a timing constraint based on the delays of the timing arcs in the at least one timing path, the local random variation information of the integrated circuit and the global variation information of the integrated circuit.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit by performing a static timing analysis on the integrated circuit, the method comprising:
loading, by a processor, a library that includes local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained based on a set of a plurality of global variation parameters of the integrated circuit;
calculating, by a static timing analysis tool, delays of timing arcs included in the integrated circuit based on the library;
determining, by the static timing analysis tool, whether at least one timing path of a plurality of timing paths included in the integrated circuit violates a timing constraint based on the delays of the timing arcs in the at least one timing path, the local random variation information of the integrated circuit and the global variation information of the integrated circuit; and
manufacturing the integrated circuit based on an integrated circuit design optimized using a result of the determination of violation of the timing constraint.

2. The method of claim 1 , wherein the global variation information of the library includes global variation values for at least two timing corners of the integrated circuit based on the set of the plurality of global variation parameters of the integrated circuit.

3. The method of claim 1 , wherein determining whether the at least one timing path violates the timing constraint includes calculating a slack of the at least one timing path based on the delays of the timing arcs included in the at least one timing path and a statistical sum of a local random variation value of the at least one timing path and a global variation value of the at least one timing path.

4. The method of claim 1 , wherein determining whether at least one timing path violates the timing constraint includes:
performing, by a graph based analysis (GBA) module, a GBA to extract a critical path from the plurality of timing paths included in the integrated circuit; and
performing, by a path based analysis (PBA) module, a PBA to determine whether the critical path violates the timing constraint.

5. The method of claim 4 , wherein performing the GBA includes:
calculating a local random variation value of each timing path in the integrated circuit by propagating a local random variation on each timing path;
calculating a global random variation value of each timing path in the integrated circuit by propagating a global variation on each timing path;
calculating a total random variation value of each timing path from a statistical sum of the local random variation value of each timing path and the global random variation value of each timing path; and
determining whether a timing path is the critical path based on the delays of the timing arcs included in each timing path and the total random variation value of each timing path.

6. The method of claim 5 , wherein the local random variation information includes local random variation values of the timing arcs, and
the local random variation value of each timing path is calculated from a root-sum-square of the local random variation values of the timing arcs included in each timing path.

7. The method of claim 5 , wherein the global variation information includes global variation values of the timing arcs, and
the global variation value of each timing path is calculated from a linear sum of the global variation values of the timing arcs included in each timing path.

8. The method of claim 7 , wherein one of the plurality of timing path includes a data path and a clock path, and
wherein the global variation value of the one timing path is calculated by applying the global variation values of the timing arcs at a fast corner of the integrated circuit with respect to one of the data path and the clock path, and by applying the global variation values of the timing arcs at a slow corner of the integrated circuit with respect to another one of the data path and the clock path.

9. The method of claim 5 , wherein the statistical sum of the local random variation value of each timing path and the global random variation value of each timing path includes a root-sum-square of the local random variation value of each timing path and the global random variation value of each timing path.

10. The method of claim 4 , wherein performing the PBA includes:
calculating a local random variation value of the critical path by calculating a root-sum-square of local random variation values of the timing arcs included in the critical path;
calculating a worst global variation value of the critical path by calculating respective slacks of the critical path at a plurality of timing corners and a nominal corner of the integrated circuit;
calculating a worst total variation of the critical path from a statistical sum of the local random variation value of the critical path and the worst global variation value of the critical path; and
determining whether the critical path violates the timing constraint based on the delays of the timing arcs included in the critical path and the worst total variation of the critical path.

11. The method of claim 10 , wherein calculating the worst global variation value of the critical path includes:
calculating the respective slacks of the critical path at the plurality of timing corners;
selecting a minimum of the calculated slacks of the critical path; and
calculating the worst global variation value of the critical path by subtracting the minimum of the calculated slacks of the critical path from a slack of the critical path at the nominal corner of the integrated circuit.

12. The method of claim 10 , wherein determining whether the critical path violates the timing constraint includes:
calculating a worst slack of the critical path based on the delays of the timing arcs included in the critical path and the worst total variation of the critical path; and
deciding that the critical path violates the timing constraint when the worst slack of the critical path has a negative value.

13. The method of claim 10 , wherein calculating the worst global variation value of the critical path includes:
calculating global variation values of the critical path at the timing corners included in the global variation information;
calculating a global variation value for at least one timing corner not included in the global variation information based on the global variation values of the critical path for at least two of the timing corners included in the global variation information; and
selecting, as the worst global variation value of the critical path, a maximum of the global variation values of the critical path at timing corners included in the global variation information and the global variation value at the timing corner not included in the global variation information.

14. The method of claim 4 , further comprising:
changing, by the static timing analysis tool, a nominal corner of the integrated circuit based on global variation values of at least two timing corners included in the global variation information, wherein the graph based analysis (GBA) is performed at the changed nominal corner, and the path based analysis (PBA) is performed at the changed nominal corner.

15. A method of manufacturing an integrated circuit by performing a static timing analysis on the integrated circuit, the method comprising:
loading, by a processor, a library including local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained ba

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Kim Moon-Su

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2217/84

  Physics · mapped topic