Integrated circuit chip design methods and systems using process window-aware timing analysis

Patent metadata

Field	Value
Publication number	US-9619609-B1
Application number	US-201514862652-A
Country	US
Kind code	B1
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Design methods and systems disclosed use a process window-aware timing analysis of an integrated circuit (IC) chip design for improved accuracy. Specifically, a process distribution for the design is defined and divided into process windows. Timing parameter adjustment factors are assigned to the process windows. A timing analysis is performed in order to acquire an initial solution for a timing parameter (e.g., delay, slack or slew). For each specific process window, this initial solution is adjusted by the predetermined timing parameter adjustment factor assigned to that specific process window. The adjusted solutions for the different process windows account for process window-to-process window variations in the widths of distribution of a process parameter (e.g., leakage power) and can be used to predict whether IC chips manufactured according the IC chip design will meet established timing requirements (e.g., required arrival times (RATs)) regardless of where they fall within the process distribution.

First claim

What is claimed is:

1. A method comprising:
dividing, by a processor, a process distribution for an integrated circuit chip design into process windows;
determining, by the processor, widths of distribution for a process parameter in the process windows, respectively, the process parameter impacting a timing parameter;
based on the widths of distribution of the process parameter, assigning, by the processor, timing parameter adjustment factors to the process windows, respectively;
performing, by the processor, a timing analysis of the integrated circuit chip design to acquire an initial solution for the timing parameter;
for each specific process window, determining, by the processor, an adjusted solution for the timing parameter by adjusting the initial solution using a specific timing parameter adjustment factor assigned to the specific process window; and,
given the adjusted solution for the timing parameter, predicting, by the processor, whether integrated circuit chips manufactured according to the integrated circuit chip design will meet a predetermined timing requirement.

2. The method of claim 1 , further comprising, when the predetermined timing requirement will not met, altering, by the processor, the integrated circuit chip design and repeating, by the processor, the determining of the widths of distribution, the assigning of the timing parameter adjustment factors, the performing of the timing analysis and the determining whether the integrated circuit chip design meets the predetermined timing requirement.

3. The method of claim 1 , further comprising, when the predetermined timing requirement will met, manufacturing integrated circuit chips according to the integrated circuit chip design.

4. The method of claim 1 , the process parameter comprising leakage power and the timing parameter comprising any of delay, slack and slew.

5. The method of claim 4 , the widths of distribution and the timing parameter adjustment factors decreasing between a first end of the process distribution associated with a relatively fast operating speed and a second end of the process distribution associated with a relatively slow operating speed.

6. The method of claim 1 , further comprising, before the dividing of the process distribution, adjusting, by the processor, manufacturing line processes in order to re-center the process distribution.

7. The method of claim 1 , further comprising, before the dividing of the process distribution, establishing, by the processor, at least one of a leakage power screen at a first end of the process distribution associated with a relatively fast operating speed and a performance screen at a second end of the process distribution associated with a relatively slow operating speed.

8. The method of claim 1 , further comprising assigning, by the processor, operating voltage ranges to the process windows so as to optimize power at a first end of the process distribution associated with a relatively fast operating speed and so as to optimize performance at a second end of the process distribution associated with a relatively slow operating speed.

9. A system comprising:
a memory storing an integrated circuit chip design and a process distribution for the integrated circuit chip design; and,
at least one processor in communication with the memory,
the at least one processor performing the following:
accessing the process distribution and dividing the process distribution into process windows;
determining widths of distribution for a process parameter in the process windows, respectively, the process parameter impacting a timing parameter;
based on the widths of distribution of the process parameter, assigning timing parameter adjustment factors to the process windows, respectively;
performing a timing analysis of the integrated circuit chip design to acquire an initial solution for the timing parameter;
for each specific process window, determining an adjusted solution for the timing parameter by adjusting the initial solution using a specific timing parameter adjustment factor assigned to the specific process window; and,
given the adjusted solution for the timing parameter, predicting whether integrated circuit chips manufactured according to the integrated circuit chip design will meet a predetermined timing requirement.

10. The system of claim 9 , the at least one processor further altering the integrated circuit chip design, when the predetermined timing requirement will not be met, and repeating the determining of the widths of distribution, the assigning of the timing parameter adjustment factors, the performing of the timing analysis and the determining whether the integrated circuit chip design meets the predetermined timing requirement.

11. The system of claim 9 , the at least one processor further releasing the integrated circuit chip design to manufacturing, when the predetermined timing requirement will be met.

12. The system of claim 9 , the process parameter comprising leakage power and the timing parameter comprising any of delay, slack and slew.

13. The system of claim 12 , the widths of distribution and the timing parameter adjustment factors decreasing between a first end of the process distribution associated with a relatively fast operating speed and a second end of the process distribution associated with a relatively slow operating speed.

14. The system of claim 9 , the at least one processor further, before the dividing of the process distribution, establishing at least one of a leakage power screen at a first end of the process distribution associated with a relatively fast operating speed and a performance screen at a second end of the process distribution associated with a relatively slow operating speed.

15. A computer program product comprising a computer readable storage medium, the computer readable storage medium storing program instructions, the program instructions being executable by a processor to cause the processor to perform a method, the method comprising:
dividing a process distribution for an integrated circuit chip design into process windows;
determining widths of distribution for a process parameter in the process windows, respectively, the process parameter impacting a timing parameter;
based on the widths of distribution of the process parameter, assigning timing parameter adjustment factors to the process windows, respectively;
performing a timing analysis of the integrated circuit chip design to acquire an initial solution for the timing parameter;
for each specific process window, determining an adjusted solution for the timing parameter by adjusting the initial solution using a specific timing parameter adjustment factor assigned to the specific process window; and,
given the adjusted solution for the timing parameter, predicting whether integrated circuit chips manufactured according to the integrated circuit chip design will meet a predetermined timing requirement.

16. The computer program product of claim 15 , the method further comprising, when the predetermined timing requirement will not be met, altering the integrated circuit chip design and repeating the determining of the widths of distribution, the assigning of the timing parameter adjustment factors, the performing of the timing analysis and the determining whether the integrated circuit chip design meets the predetermined timing requirement.

17. The computer program product of claim 15 , the method further comprising, when the predetermined timing requirement will be met, manufacturing integrated circuit chips according to the i

Assignees

• Globalfoundries Inc

Inventors

• Bickford Jeanne P
• Foreman Eric A
• Lichtensteiger Susan K
• Kuemerle Mark W
• Hemmett Jeffrey G

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2217/78

  Physics · mapped topic