Coherent memory interleaving with uniform latency

Patent metadata

Field	Value
Publication number	US-9977750-B2
Application number	US-201414568433-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.

First claim

What is claimed is:

1. A data processing system, comprising:
a network of interconnected switch points having a plurality of edge switch points located at an edge of the network;
a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers;
a plurality of target memory controllers; and
a crossbar switch coupled between the plurality of network interface controllers and the plurality of target memory controllers, wherein the crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target memory controllers, wherein the plurality of network interface controllers are coupled between the plurality of edge switch points and the crossbar switch.

2. The data processing system of claim 1 , wherein the read/write signals communicated by the crossbar switch comprise read/write access requests and corresponding read/write data.

3. The data processing system of claim 2 , wherein all read/write access requests directed to any target memory controller of the plurality of target memory controllers generated by a processing unit at a first switch point of the network are transmitted through a same path of switch points from the first switch point to a first edge switch point of the plurality of edge switch points.

4. The data processing system of claim 3 , wherein a first read/write access request generated by the processing unit at the first switch point and transmitted to the first edge switch point is communicated to a first target memory controller of the plurality of target memory controllers through the crossbar switch, and a second read/write access request generated by the processing unit at the first switch point and transmitted to the first edge switch point is communicated to a second target memory controller of the plurality of target memory controllers through the crossbar switch.

5. The data processing system of claim 1 , further comprising a snoop interconnect between each network interface controller and a corresponding target memory controller of the plurality of target memory controllers, wherein the snoop interconnect is configured to communicate snoop messages outside the crossbar switch.

6. The data processing system of claim 5 , wherein the snoop messages are communicated between each network interface controller and a snoop network.

7. The data processing system of claim 1 , further comprising a coherency response interconnect between each network interface controller and the corresponding target memory controller, wherein the coherency response interconnect is configured to communicate coherency responses outside the crossbar switch.

8. The data processing system of claim 7 , wherein the coherency responses are communicated between each network interface and a coherency response network.

9. The data processing system of claim 1 , wherein each target memory controller of the plurality of target memory controllers comprises a global ordering point and a memory controller, wherein the global ordering point is configured to determine an order of memory accesses performed by the memory controller.

10. The data processing system of claim 9 , further comprising a memory coupled to a memory controller of a target memory controller of the plurality of target memory controllers.

11. The data processing system of claim 9 , further comprising a memory coupled to each memory controller.

12. A method comprising:
generating a first read/write access request by a first processing unit coupled to a first switch point of a network of interconnected switch points in a data processing system, wherein the network includes a plurality of edge switch points located at an edge of the network;
transmitting the first read/write access request through a first path of the network to a first edge switch point via a second switch point of the network of interconnected switch points, the second switch point is not at the edge of the network;
determining a first destination target memory controller of the first read/write access request; and
transmitting the first read/write access request through a crossbar switch from the first edge switch point to the first destination target memory controller.

13. The method of claim 12 , wherein the first path of the network comprises one or more switch points of the network.

14. The method of claim 12 , further comprising:
generating, by the first processing unit coupled to the first switch point of the network, a second read/write access request having a different destination than the first read/write access request;
transmitting the second read/write access request through the first path of the network to the first edge switch point;
determining a second destination target memory controller of the second read/write access request, wherein the second destination target memory controller is different from the first target memory controller; and
transmitting the second read/write access request through the crossbar switch from the first edge switch point to the second destination target memory controller.

15. The method of claim 12 , further comprising:
providing a snoop message from the first destination target memory controller to the first edge switch point without transmitting the snoop message through the crossbar switch; and
providing the snoop message from the first edge switch point to a snoop network of the data processing system.

16. The method of claim 15 , further comprising:
receiving, at the first edge switch point, a coherency response to the first read/write access from a coherency response network of the of the data processing system; and
providing the coherency response to the first destination target memory controller without transmitting the coherency response through the crossbar switch.

17. The method of claim 12 , further comprising:
transmitting read/write data corresponding to the first read/write access request between the first switch point and the first edge switch point, wherein the read/write data is transmitted along the first path; and
transmitting the read/write data through the crossbar switch between the first edge switch point and the destination target memory controller.

18. The method of claim 17 , further comprising:
when the first read/write access request is a write request, providing the read/write data to a first memory coupled to the first destination target memory controller; and
when the first read/write access request is a read request, receiving the read/write data from the first memory.

19. A data processing system, comprising:
a network of interconnected switch points having a plurality of edge switch points located at an edge of the network;
a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers;
a plurality of target memory controllers;
a crossbar switch coupled between the plurality of network interface controllers and the plurality of target memory controllers, wherein the crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target memory controllers, wherein the plurality of network interface controllers are coupled betw

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Deshpande Sanjay R
• Larson John E

Classifications

• G06F13/1684

  using multiple buses · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F13/161 Primary

  with latency improvement · CPC title