Method, information processing apparatus, and computer readable medium

Patent metadata

Field	Value
Publication number	US-9977720-B2
Application number	US-201615064747-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 11, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method includes: causing at least three processors to perform a same process; extracting, when one of the at least three processors outputs different operational information generated by performing the same process, majority processors with which outputted operational information are the same and a minority processor with which different operational information is outputted; and controlling one of the two redundant processors to output a result of the same process.

First claim

What is claimed is:

1. A method executed by a computer, the method comprising:
causing a first processor and each processor of a processor group to perform a process, the first processor being set as an operation processor;
comparing first operational information with each operational information generated by each processor of the processor group in the process, the first operational information generated by the first processor in the process;
when the first operational information is different from second operational information generated by each of a first plurality of processors of the processor group in the process, setting one of the first plurality of processors as the operation processor instead of the first processor;
adding the first processor to the processor group;
controlling the one of the first plurality of processors to output a result of the process; and
after the adding, when a number of times that the first processor generates operational information different from third operational information generated by each of a second plurality of processors of the processor group in other processes is no less than a value, excluding the first processor from the processor group.

2. The method according to claim 1 , wherein the first operational information and the second operational information include at least one of a writing address of data, a value of data to be written, a reading address of data, and a value of data that is read out in the process.

3. The method according to claim 1 , wherein the first operational information and the second operational information are acquired by capturing data transferred through a bus coupling to the first processor and each processor of the processor group.

4. The method according to claim 1 , wherein in the causing, the process is performed by each processor of the processor group with a certain delay after a timing at which the first processor performs the process.

5. The method according to claim 1 , wherein a second processor of the processor group is excluded from the processor group when a period or a number of times that the second processor generates operational information different from operational information generated by each of the first plurality of processors in processes is no less than a certain period or a certain value.

6. The method according to claim 1 , further comprising:
switching bus connection from the first processor to each processor of the processor group when the setting is executed.

7. The method according to claim 1 , wherein the one of the first plurality of processors which is set as the operation processor is selected based on priority order assigned to each of the first plurality of processors.

8. An information processing apparatus, comprising:
control circuitry configured to
cause a first processor and each processor of a processor group to perform a process, the first processor being set as an operation processor;
compare first operational information with each operational information generated by each processor of the processor group in the process, the first operational information generated by the first processor in the process;
when the first operational information is different from second operational information generated by each of a first plurality of processors of the processor group in the process, set one of the first plurality of processors as the operation processor instead of the first processor;
add the first processor to the processor group;
control the one of the first plurality of processors to output a result of the process; and
after the first processor is added to the processor group, when a number of times that the first processor generates operational information different from third operational information generated by each of a second plurality of processors of the processor group in other processes is no less than a value, exclude the first processor from the processor group.

9. The information processing apparatus according to claim 8 , wherein the first operational information and the second operational information include at least one of a writing address of data, a value of data to be written, a reading address of data, and a value of data that is read out in the process.

10. The information processing apparatus according to claim 8 , wherein the first operational information and the second operational information are acquired by capturing data transferred through a bus coupling to the first processor and each processor of the processor group.

11. The information processing apparatus according to claim 8 , wherein the process is performed by each processor of the processor group with a certain delay after a timing at which the first processor performs the process.

12. The information processing apparatus according to claim 8 , wherein a second processor of the processor group is excluded from the processor group when a period or a number of times that the second processor generates operational information different from operational information generated by each of the first plurality of processors in processes is no less than a certain period or a certain value.

13. The information processing apparatus according to claim 8 , wherein the control circuitry is configured to switch bus connection from the first processor to each processor of the processor group when the setting is executed.

14. The information processing apparatus according to claim 8 , wherein the one of the first plurality of processors which is set as the operation processor is selected based on priority order assigned to each of the first plurality of processors.

15. A non-transitory computer readable medium having stored therein a program that causes a computer to execute a control process, the control process comprising:
causing a first processor and each processor of a processor group to perform a process, the first processor being set as an operation processor;
comparing first operational information with each operational information generated by each processor of the processor group in the process, the first operational information generated by the first processor in the process;
when the first operational information is different from second operational information generated by each of a first plurality of processors of the processor group in the process, setting one of the first plurality of processors as the operation processor instead of the first processor;
adding the first processor to the processor group;
controlling the one of the first plurality of processors to output a result of the process; and
after the adding, when a number of times that the first processor generates operational information different from third operational information generated by each of a second plurality of processors of the processor group in other processes is no less than a value, excluding the first processor from the processor group.

16. The non-transitory computer readable medium according to claim 15 , wherein a second processor of the processor group is excluded from the processor group when a period or a number of times that the second processor generates operational information different from operational information generated by each of the first plurality of processors in processes is no less than a certain period or a certain value.

17. The non-transitory computer readable medium according to claim 15 , wherein the control process further comprising:
switching bus connection from the first processor to each processor of the processor group when the setting is executed.

Assignees

• Fujitsu Ltd

Inventors

• Fujimoto Koki

Classifications

• G06F11/184 Primary

  where the redundant components implement processing functionality · CPC title

• G06F11/1695

  which are operating with time diversity · CPC title