Selecting master time of day for maximum redundancy

Patent metadata

Field	Value
Publication number	US-9804938-B2
Application number	US-201514930021-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Oct 11, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure requiring a topology switch, the system re-configures to the second TOD topology.

First claim

The invention claimed is:

1. A method implemented by an information handling system that includes a memory and a plurality of processors, the method comprising:
identifying an amount of functioning cores within each of a plurality of processors;
selecting a first one of the plurality of processors as a master time of day (TOD) processor in a master TOD topology based upon determining that the first processor has a largest amount of functioning cores out of the plurality of processors, wherein the first processor is located on a first node;
assigning a second one of the plurality of processors as an alternate master TOD processor to a backup TOD topology based upon determining that the second processor is on a second node that is different than the first node;
configuring the information handling system to the master TOD topology; and
in response to detecting a TOD failure on the master TOD topology, re-configuring the information handling system to the backup TOD topology.

2. The method of claim 1 wherein the selection of the master TOD processor further comprises:
detecting that the first processor is directly connected to a first oscillator; and
performing the selection of the first processor as the master TOD processor based upon the first processor having the largest amount of functioning cores and directly connected to the oscillator.

3. The method of claim 2 wherein the assigning of the alternate master TOD processor further comprises:
identifying a subset of the plurality of processors that are each located on a different node than the first node and directly connected to a different oscillator than the first oscillator;
identifying an amount of functioning cores in each of the processors in the subset of processors; and
performing the assigning of the second processor as the alternate master TOD processor based upon determining that the second processor has a largest amount of functioning cores out of the subset of processors.

4. The method of claim 1 wherein the re-configuring designates the alternate master TOD processor as a new master TOD processor and, subsequent to the re-configuring, the method further comprises:
constructing a new backup TOD topology, wherein the new backup TOD topology further comprises:
in response to determining that one or more third processors exist, from the plurality of processes, that are each part of a different node than the new master TOD processor and a directly connected to a different oscillator than the new master TOD's oscillator:
selecting one of the third processors that has a largest amount of functioning cores out of the one or more third processors; and
assigning the selected third processor to the new backup TOD topology.

5. The method of claim 4 further comprising:
in response to determining that the one or more third processors do not exist, determining whether one or more fourth processors exist, from the plurality of processes, that are a directly connected to the different oscillator than the new master TO D's oscillator:
selecting one of the fourth processors that has a largest amount of functioning cores out of the one or more fourth processors; and
assigning the selected fourth processor to the new backup TOD topology.

6. The method of claim 5 further comprising:
in response to determining that the one or more fourth processors do not exist, determining whether one or more fifth processors exist, from the plurality of processes, that are each part of the different node than the new master TOD processor and directly connected to an oscillator:
selecting one of the fifth processors that has a largest amount of functioning cores out of the one or more fifth processors; and
assigning the selected fifth processor to the new backup TOD topology.

7. The method of claim 6 further comprising:
in response to determining that the one or more fifth processors do not exist, determining whether one or more sixth processors exist, from the plurality of processes, that are a directly connected to an oscillator:
selecting one of the fifth processors that has a largest amount of functioning cores out of the one or more fifth processors; and
assigning the selected fifth processor to the new backup TOD topology.

Assignees

• IBM

Inventors

• Chowdhary Manish Kumar
• Kodihalli Deepak

Classifications

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F2201/805

  Real-time · CPC title

• G06F11/2028 Primary

  eliminating a faulty processor or activating a spare · CPC title

• G06F11/2017

  where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089) · CPC title

• G06F11/2038

  with a single idle spare processing component · CPC title