Memory system

Patent metadata

Field	Value
Publication number	US-9977605-B2
Application number	US-201615292314-A
Country	US
Kind code	B2
Filing date	Oct 13, 2016
Priority date	Oct 16, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a high-capacity memory, which has a lower latency than the second memory and operates as a cache memory for the second memory, and a high-speed memory, which has a lower latency than the high-capacity memory and operates as a cache memory for the high-capacity memory,
wherein the first memory controller includes a high-capacity memory cache controller suitable for controlling the high-capacity memory to store data, and a high-speed memory cache controller suitable for controlling the high-speed memory to store data,
wherein the second memory controller and the second memory communicate with each other through an input/output bus,
wherein the high-speed memory cache controller and the high-speed memory communicate with each other through a first input/output bus, which is a part of the input/output bus, in a high-speed operation mode,
wherein the high-capacity memory cache controller and the high-capacity memory communicate with each other through a second input/output bus, which is another part of the input/output bus, in a high-capacity operation mode, and
wherein the high-capacity memory caches data of the second memory through the second input/output bus under a control of the second memory controller and the high-capacity memory cache controller in the high-speed operation mode.

2. The memory system of claim 1 , wherein the second memory controller includes:
a handshaking interface suitable for transferring the signal between the second memory device and the processor; and
a register suitable for temporarily storing data read out from the second memory.

3. The memory system of claim 1 , wherein the at least one of values of the handshaking information field indicates the signal one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

4. The memory system of claim 3 , wherein the data request signal includes a command and an address for the second memory device.

5. The memory system of claim 3 ,
wherein the second memory controller includes a storage unit and
wherein the second memory controller reads data from the second memory and temporarily stores the read data in the storage unit in response to the data request signal.

6. The memory system of claim 5 , wherein the second memory controller provides the data ready signal to the processor when the second memory controller temporarily stores the read data in the storage unit in response to the data request signal.

7. The memory system of claim 6 , wherein the processor provides the session start signal to receive the read data temporarily stored in the storage unit in response to the data ready signal.

8. The memory system of claim 1 , wherein the first memory device is a volatile memory device.

9. The memory system of claim 1 , wherein the second memory device is a nonvolatile memory device.

10. The memory system of claim 9 , wherein the nonvolatile memory device is a nonvolatile random access memory device.

11. A memory system comprising:
a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data;
a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and
a processor suitable for accessing the first and second memories,
wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a high-capacity memory, which has a lower latency than the second memory and operates as a cache memory for the second memory, and a high-speed memory, which has a lower latency than the high-capacity memory and operates as a cache memory for the high-capacity memory,
wherein the first memory controller includes a high-capacity memory cache controller suitable for controlling the high-capacity memory to store data, and a high-speed memory cache controller suitable for controlling the high-speed memory to store data,
wherein the second memory controller and the second memory communicate with each other through an input/output bus,
wherein the high-speed memory cache controller and the high-speed memory communicate with each other through a first input/output bus, which is a part of the input/output bus, in a high-speed operation mode,
wherein the high-capacity memory cache controller and the high-capacity memory communicate with each other through a second input/output bus, which is another part of the input/output bus, in a high-capacity operation mode, and
wherein the high-capacity memory caches data of the second memory through the second input/output bus under a control of the second memory controller and the high-capacity memory cache controller in the high-speed operation mode.

12. The memory system of claim 11 , wherein the second memory controller includes:
handshaking interface suitable for transferring the signal between the second memory device and the processor; and
a register suitable for temporarily storing data read out from the second memory.

13. The memory system of claim 11 , wherein the at least one of values of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

14. The memory system of claim 13 , wherein the data request signal includes a command and an address for the second memory device.

15. The memory system of claim 13 ,
wherein the second memory controller includes a storage unit, and
wherein the second memory controller reads data from the second memory and temporarily stores the read data in the storage unit in response to the data request signal.

16. The memory system of claim 15 , wherein the second memory controller provides the data ready signal to the processor when the second memory controller temporarily stores the read data in the storage unit in response to the data request signal.

17. The memory system of claim 16 , wherein the processor provides the session start signal to receive the read data temporarily stored in the storage unit in response to the data ready signal.

18. The memory system of claim 11 , wherein the first memory device is a volatile memory device.

19. The memory system of claim 11 , wherein the second memory device is a nonvolatile memory device.

20. The memory system of claim 19 , wherein the nonvolatile memory device is a nonvolatile random access memory device

Assignees

• Sk Hynix Inc

Inventors

• Kim Min-Chang
• Kim Chang-Hyun
• Lee Do-Yun
• Lee Jae-Jin
• Jung Hoe-Kwon

Classifications

• G06F2212/60

  Details of cache memory · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0622

  in relation to access · CPC title