Method and apparatus for setting an I/O bandwidth-based processor frequency floor

Patent metadata

Field	Value
Publication number	US-9977482-B2
Application number	US-201113992706-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

First claim

What is claimed is:

1. An apparatus comprising:
a power control unit to manage power in a computer processor, the power control unit including:
a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor, wherein the plurality of communication ports include input/output modules and processor interconnect modules, wherein
the transaction rate data is provided by a set of counters in each communication port, wherein the counters are for transmit and receive for the processor interconnect modules and the counters are for read and write for the input/output modules; and
a frequency control logic module coupled to the data collection module, the frequency control logic module to
calculate a minimum processor interconnect frequency for the computer processor based on the transaction rate data obtained from the plurality of communication ports, the minimum processor interconnect frequency enabling the communication ports to handle traffic without significant added latency due to a low power or low frequency state of the computer processor caused by inactivity of cores of the computer processor; and
override a processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

2. The apparatus of claim 1 , wherein the frequency control logic module sets a system clock to the calculated minimum processor interconnect frequency.

3. The apparatus of claim 1 , wherein the data collection module polls the plurality of communication modules to obtain the transaction data.

4. The apparatus of claim 1 , wherein the frequency control logic module compares a maximum transaction rate of the plurality of communication ports to a threshold value to determine whether to override the processor frequency.

5. The apparatus of claim 1 , wherein the frequency control logic module calculates the minimum processor interconnect frequency as a maximum of a set of processor interconnect frequency floors for the plurality of communication ports.

6. The apparatus of claim 1 , wherein the data collection module polls the plurality of communication ports at regular intervals over message channel as a bulk read.

7. The apparatus of claim 1 , wherein the minimum processor interconnect frequency is calculated as A+MAX(B*input/output module counter values, C* processor interconnect module counter values), where A, B and C are programmable constants.

8. A computer system comprising:
a memory device to store data;
a first multi-core processor to perform a first set of programmed operations; and
a second multi-core processor coupled to the memory and first multi-core processor to perform a second set of programmed operations, the second multi-core processor including a power control unit to manage power in a computer processor including:
a data collection module to obtain transaction rate data from a plurality of communication ports in the second multi-core processor wherein the plurality of communication ports include input/output modules and processor interconnect modules, wherein
the transaction rate data is provided by a set of counters in each communication port, wherein the counters are for transmit and receive for the processor interconnect modules and the counters are for read and write for the input/output modules, and
a frequency control logic module coupled to the data collection module, the frequency control logic module to
calculate a minimum processor interconnect frequency for the computer processor based on the transaction rate data obtained from the plurality of communication ports, the minimum processor interconnect frequency enables the communication ports to handle traffic without significant added latency due to a low power or low frequency state of the computer processor caused by inactivity of cores of the computer processor; and
override a processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

9. The computer system of claim 8 , wherein the frequency control logic module sets a system clock to the calculated minimum processor interconnect frequency.

10. The computer system of claim 8 , wherein the data collection module polls the plurality of communication modules to obtain the transaction data.

11. The computer system of claim 8 , wherein the frequency control logic module compares a maximum transaction rate of the plurality of communication ports to a threshold value to determine whether to override the processor frequency.

12. The computer system of claim 8 , wherein the frequency control logic module calculates the minimum processor interconnect frequency as a maximum of a set of processor interconnect frequency floors for the plurality of communication ports.

13. The computer system of claim 8 , wherein the data collection module polls the plurality of communication ports at regular intervals over message channel as a bulk read.

14. A method comprising:
initiating monitoring of a communication port by a power control unit (PCU) wherein the communication port is one of an input/output module and a processor interconnect module;
obtaining communication port transaction data from the communication port, wherein the communication transaction rate data is provided by a set of counters in the communication port, wherein the counters are for transmit and receive for the processor interconnect module and the counters are for read and write for the input/output module;
calculating a minimum processor interconnect frequency for a processor on a die-shared by the PCU, the minimum processor interconnect frequency enabling the communication port to handle traffic without significant added latency due to a low power or low frequency state of the processor caused by inactivity of cores of the processor; and
overriding a processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

15. The method of claim 14 , further comprising:
checking whether the processor frequency meets the minimum processor interconnect frequency.

16. The method of claim 14 , further comprising:
setting a system clock to the minimum processor interconnect frequency.

17. The method of claim 14 , further comprising:
polling the communication port to obtain the communication port transaction data.

18. The method of claim 14 , further comprising:
comparing a maximum transaction rate of a plurality of communication ports to a threshold value to determine whether to override the processor frequency.

Assignees

• Varma Ankush
• Steiner Ian M
• Sistla Krishnakanth V
• Bace Matthew M
• Garg Vivek
• Rowland Martin T
• Wilder Jeffrey S
• Intel Corp

Inventors

• Varma Ankush
• Steiner Ian M
• Sistla Krishnakanth V
• Bace Matthew M
• Garg Vivek
• Rowland Martin T
• Wilder Jeffrey S

Classifications

• G06F13/382 Primary

  using universal interface adapter · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title