Successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9973202-B2
Application number	US-201715714772-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 20, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

First claim

What is claimed is:

1. A successive approximation register analog-to-digital converter, comprising:
a first capacitance digital-to-analog converter (CDAC) having an input terminal to which an analog signal is input and an output terminal from which an output signal is output;
a first comparator configured to compare a voltage input to an input terminal thereof, which is connected to the output terminal of the first CDAC, with a reference voltage;
a first successive approximation register (SAR) circuit configured to control the first CDAC based on an output of the first comparator and generate a digital output of the successive approximation register analog-to-digital converter based on the output of the first comparator;
a second CDAC having an input terminal to which the output signal from the first CDAC is input and an output terminal from which an output signal is output;
a second comparator configured to compare a voltage input to an input terminal thereof, which is connected to the output terminal of the second CDAC, with a reference voltage;
a second SAR circuit configured to control the second CDAC based on an output of the second comparator and having an output terminal from which a digital signal representing a residual voltage of the output signal of the first CDAC is output; and
a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

2. The successive approximation register analog-to-digital converter according to claim 1 , wherein the feedback circuit includes:
a first delay circuit to which the digital signal is input;
a second delay circuit to which an output signal from the first delay circuit is input;
a third CDAC having an input terminal to which the output signal from the first delay circuit is input;
a fourth CDAC having an input terminal to which an output signal from the second delay circuit is input; and
an adding circuit configured to combine output signals from at least the third CDAC and the fourth CDAC to generate the residual signal.

3. The successive approximation register analog-to-digital converter according to claim 2 , wherein each of first and second delay circuits includes a flip-flop circuit and a register circuit controlled by a control signal from the second CDAC.

4. The successive approximation register analog-to-digital converter according to claim 2 , wherein the third CDAC includes:
an output terminal through which the output signal of the third CDAC is output;
a first capacitor having a first end electrically connected to the output terminal;
a second capacitor having a first end electrically connected to the output terminal;
a reference voltage line;
a ground voltage line;
a first switch controlled by an output of the first delay circuit to electrically connect a second end of the first capacitor to one of the reference voltage line and the ground voltage line; and
a second switch controlled by an output of the first delay circuit to electrically connect a second end of the second capacitor to one of the reference voltage line and the ground voltage line.

5. The successive approximation register analog-to-digital converter according to claim 2 , wherein the feedback circuit includes:
a first delay circuit to which the digital signal is input;
a second delay circuit to which an output signal from the first delay circuit is input;
a first coefficient circuit configured to multiply the output signal from the first delay circuit by a first multiplier;
a second coefficient circuit configured to multiply an output signal from the second delay circuit by a second multiplier;
an adding circuit configured to combine output signals from at least the first coefficient circuit and the second coefficient circuit; and
a third CDAC having an input terminal to which an output signal from the adding circuit is input and an output terminal from which the residual signal is output.

6. The successive approximation register analog-to-digital converter according to claim 5 , wherein each of first and second delay circuits includes a flip-flop circuit and a register circuit controlled by a control signal from the second CDAC.

7. The successive approximation register analog-to-digital converter according to claim 5 , wherein the third CDAC includes:
an output terminal through which the output signal of the third CDAC is output;
a first capacitor having a first end electrically connected to the output terminal;
a second capacitor having a first end electrically connected to the output terminal;
a reference voltage line;
a ground voltage line;
a first switch controlled by an output of the adding circuit to electrically connect a second end of the first capacitor to one of the reference voltage line and the ground voltage line; and
a second switch controlled by an output of the adding circuit to electrically connect a second end of the second capacitor to one of the reference voltage line and the ground voltage line.

8. The successive approximation register analog-to-digital converter according to claim 1 , wherein the residual signal is output to the first CDAC two or more cycles after the output signal from the first CDAC was supplied to the second CDAC.

Assignees

• Toshiba Kk

Inventors

• Yoshioka Kentaro
• Furuta Masanori
• Kubota Hiroshi

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/0854

  of quantisation noise · CPC title

• H03M1/0656

  in the time domain, e.g. using intended jitter as a dither signal · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title