Configurable capacitor arrays and switched capacitor circuits

Patent metadata

Field	Value
Publication number	US-9973200-B2
Application number	US-201715418381-A
Country	US
Kind code	B2
Filing date	Jan 27, 2017
Priority date	Nov 24, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.

First claim

What is claimed is:

1. An integrator circuit comprising:
an amplifier circuit;
a first capacitor branch including a first plurality of capacitors, the first capacitor branch configured to couple to an input signal and to an input of the amplifier circuit;
a second capacitor branch including a second plurality of capacitors, the second capacitor branch configured to couple to the input of the amplifier circuit and to an output of the amplifier circuit;
at least one switch to selectively couple a capacitor plate of the first capacitor branch and a capacitor plate of the second capacitor branch to the output of the amplifier circuit; and
a third capacitor branch comprising a third plurality of capacitors, wherein the third plurality of capacitors is configurable to provide one of a plurality of analog functions.

2. The integrator circuit of claim 1 , wherein the amplifier circuit comprises an operational amplifier.

3. The integrator circuit of claim 1 , wherein the input of the amplifier circuit comprises a negative input and a positive input.

4. The integrator circuit of claim 3 , wherein the first capacitor branch and the second capacitor branch are configured to couple to the negative input of the amplifier circuit and wherein the positive input of the amplifier circuit is configured to couple to a reference signal.

5. The integrator circuit of claim 1 , further comprising a plurality of switches configurable to selectively couple the first capacitor branch to the input signal and selectively couple the first capacitor branch to a reference signal.

6. The integrator circuit of claim 5 , wherein the plurality of switches is further configurable to selectively couple the first capacitor branch to the output of the amplifier circuit and selectively couple the second capacitor branch to the output of the amplifier circuit.

7. The integrator circuit of claim 1 , wherein the first capacitor branch further comprises a first plurality of switches, wherein the first plurality of switches is configurable to selectively couple a first plate of each capacitor of the first plurality of capacitors to the input signal and selectively couple the first plate of each capacitor of the first plurality of capacitors to a reference signal.

8. The integrator circuit of claim 1 , wherein the second capacitor branch further comprises a second plurality of switches, wherein the second plurality of switches is configurable to selectively couple a first plate of each capacitor of the second plurality of capacitors to the output of the amplifier circuit.

9. The integrator circuit of claim 1 , wherein a second plate of each capacitor of the first plurality of capacitors is configured to couple to a second plate of each capacitor of the second plurality of capacitors.

10. A configurable circuit comprising:
a plurality of capacitor branches including a first capacitor branch comprising a first array of capacitors, a second capacitor branch comprising a second array of capacitors, and a third capacitor branch comprising a third array of capacitors;
an amplifier circuit configured to couple to the first capacitor branch and the second capacitor branch; and
a plurality of switches coupled to the first and second capacitor branches, wherein the first capacitor branch and the second capacitor branch are configurable using the plurality of switches to accumulate charge on the second array of capacitors based on an input voltage coupled to the first array of capacitors, wherein the amplifier circuit is configured to use the accumulated charge to generate an output voltage that is based on the input voltage, and wherein the third array of capacitors is configurable alone or in combination with one or more of the first array of capacitors and the second array of capacitors to provide one of a plurality of analog functions.

11. The configurable circuit of claim 10 , wherein the amplifier circuit comprises an operational amplifier including a first input and a second input, wherein the output voltage is greater than the input voltage.

12. The configurable circuit of claim 11 , wherein the first capacitor branch and the second capacitor branch couple to the first input of the operational amplifier and wherein the second input of the operational amplifier couples to a reference voltage.

13. The configurable circuit of claim 10 , wherein the plurality of switches is configurable to selectively couple the first capacitor branch to the input voltage and selectively couple the first capacitor branch to a reference voltage.

14. The configurable circuit of claim 13 , wherein the plurality of switches is further configurable to selectively couple the first capacitor branch to the output of the amplifier circuit and selectively couple the second capacitor branch to the output of the amplifier circuit.

15. The configurable circuit of claim 10 , wherein the first capacitor branch further comprises a first plurality of switches, wherein the first plurality of switches is configurable to selectively couple a first plate of each capacitor of the first array of capacitors to the input voltage and selectively couple the first plate of each capacitor of the first array of capacitors to a reference voltage.

16. The configurable circuit of claim 10 , wherein the second capacitor branch further comprises a second plurality of switches, wherein the second plurality of switches is configurable to selectively couple a first plate of each capacitor of the second array of capacitors to the output of the amplifier circuit.

17. A method comprising:
providing first one or more switch signals to selectively couple first plates of first capacitor branch capacitors to each of an input signal and a reference signal;
providing second one or more switch signals to selectively couple first plates of second capacitor branch capacitors to an output of an electronic amplifier,
providing third one or more switch signals to selectively couple second plates of the first capacitor branch capacitors and second plates of the second capacitor branch capacitors to the output of the electronic amplifier;
accumulating charge on the second capacitor branch capacitors, based on the input signal being selectively coupled to the first plates of the first capacitor branch capacitors; and
when the second plates of the first capacitor branch capacitors and second plates of the second capacitor branch capacitors are coupled to an input of electronic amplifier, using the electronic amplifier to generate an output signal that is based on the input signal.

18. The method of claim 17 , wherein using the electronic amplifier to generate the output signal includes using an operational amplifier, wherein the output signal is greater than the input signal.

19. The method of claim 17 , further comprising configuring one or more of the first capacitor branch capacitors and the second capacitor branch capacitors to, at least in part, provide an analog circuit selected from the group consisting of a delta-sigma analog to digital converter, a digital-to-analog converter; a programmable gain amplifier, a high-Q biquad, a summing circuit; an integrator, a mixing circuit, and a sample/hold comparator.

Assignees

• Cypress Semiconductor Corp

Inventors

• Johal Jaskarn Singh
• Hancioglu Erhan
• Leong Renee
• Kutz Harold M
• Thiagarajan Eashwar
• Ozbek Onur

Classifications

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03G3/20

  Automatic control ({H03G3/005 takes precedence;} combined with volume compression or expansion H03G7/00) · CPC title

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title

• H03H19/004

  Switched capacitor networks · CPC title

• G06G7/14 Primary

  for addition or subtraction  (of vector quantities G06G7/22  {; computing the average by addition; differential amplifiers H03F3/45}) · CPC title