Circuits for digital and analog controlled oscillators

Patent metadata

Field	Value
Publication number	US-9973176-B2
Application number	US-201414583679-A
Country	US
Kind code	B2
Filing date	Dec 27, 2014
Priority date	Dec 27, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply voltage for the circuit. The ring oscillator may be formed from inverters. The regulator may use a single transistor between the first node and a second node for powering the oscillator. The K compensation circuit may be used to provide to the oscillator a variable capacitive load that is dependent on the supply at the first supply node, and it may drag oscillator frequency down when the first node supply goes up.

First claim

What is claimed is:

1. A circuit, comprising:
a first node to provide a supply voltage for the circuit;
a ring oscillator comprising inverters, wherein the ring oscillator includes a second node which is to receive a power supply for the ring oscillator;
a power supply voltage regulator with a non-cascade transistor connected to the first node and the second node for powering the ring oscillator; and
a compensation circuit to provide to the ring oscillator a variable capacitive load that is dependent on the supply voltage at the first node, wherein the compensation circuit is to drag oscillator frequency down when the supply voltage on the first node goes up.

2. The circuit of claim 1 , wherein the power supply voltage regulator comprises an RC filter.

3. The circuit of claim 1 , in which the variable capacitive load is controlled through a replica transistor of the non-cascade transistor from the regulator.

4. The circuit of claim 1 , in which the ring oscillator is part of a DCO.

5. The circuit of claim 1 , in which the ring oscillator comprises tuning capacitors for controllably adjusting the oscillator frequency.

6. The circuit of claim 5 , in which the tuning capacitors when at the height of their range are at least 5 times greater than the variable capacitive load when seen substantially by the ring oscillator.

7. The circuit of claim 1 , in which at least one P-type transistor is coupled between the first node and the variable capacitive load to control how much capacitance is seen by the ring oscillator.

8. An apparatus, comprising:
a processor having an IO interface including a PLL circuit that includes:
a first node to provide a supply voltage for the circuit;
a ring oscillator comprising inverters, wherein the ring oscillator includes a second node which is to receive a power supply for the ring oscillator;
a power supply voltage regulator with a non-cascade transistor connected to the first node and the second node for powering the ring oscillator; and
a compensation circuit to provide to the ring oscillator a variable capacitive load that is dependent on the supply voltage at the first node, wherein the compensation circuit is to drag oscillator frequency down when the supply voltage on the first node goes up; and

a network interface device coupled to the processor through the 10 interface to couple the processor to a network.

9. The apparatus of claim 8 , wherein the power supply voltage regulator comprises an RC filter.

10. The apparatus of claim 8 , in which the variable capacitive load is controllable through a replica transistor of the non-cascade transistor from the regulator.

11. The apparatus of claim 8 , in which the ring oscillator is part of a DCO.

12. The apparatus of claim 8 , in which the ring oscillator tuning capacitors for controllably adjusting the oscillator frequency.

13. The apparatus of claim 12 , in which the tuning capacitors when at the height of their range are at least 5 times greater than the variable capacitive load when seen substantially by the ring oscillator.

14. The apparatus of claim 8 , in which at least one P-type transistor is coupled between the first node and the variable capacitive load to control how much capacitance is seen by the ring oscillator.

15. The apparatus of claim 8 , in which the processor is an SoC.

16. An apparatus comprising:
an oscillator;
a power supply voltage regulator comprising:
a input supply node to receive an input power supply;
an output supply node to provide an output power supply, wherein the output supply node is connected to a power supply node of the oscillator;
a transistor connected to the input and output supply nodes; and
a tunable resistor coupled to a gate terminal of the transistor via a filter;

a circuit to receive an output of the filter and to adjust loading conditions of a stage of the oscillator, wherein the circuit is to drag oscillator frequency of the oscillator when the input power supply on the input supply node goes up; and
a logic to control operation of the circuit.

17. The apparatus of claim 16 , wherein the oscillator is a digitally controlled oscillator (DCO).

18. The apparatus of claim 16 comprises a phase locked loop (PLL) circuit coupled to the oscillator.

19. The apparatus of claim 16 , wherein the circuit is to increase loading condition of the stage when the input power supply on the input supply node rises.

20. The apparatus of claim 16 , wherein the transistor is a non-cascade n-type transistor.

21. An apparatus comprising:
a input supply node to receive an input power supply;
an output supply node to provide an output power supply, wherein the output supply node is to be connected to a power supply node of an oscillator;
a non-cascade transistor connected to the input and output supply nodes;
a tunable resistor coupled to a gate terminal of the non-cascade transistor via a filter; and
a circuit to receive an output of the filter and to adjust loading conditions of a stage of the oscillator, wherein the circuit is to drag oscillator frequency of the oscillator when the input power supply on the input supply node goes up.

22. The apparatus of claim 21 , wherein the non-cascade transistor, tunable resistor and the filter are part of a power supply voltage regulator.

23. The apparatus of claim 21 , wherein the filter is to couple to a series combination of a transistor and a compensation circuit.

24. The apparatus of claim 23 , wherein the transistor is coupled to another transistor which is coupled in series with a capacitor, and wherein the capacitor is coupled to the oscillator.

25. The apparatus of claim 21 comprises:
a logic to control operation of the circuit.

Assignees

• Intel Corp

Inventors

• Li Shenggao
• Gowder Sujatha B

Classifications

• H03B5/124

  the means comprising a voltage dependent capacitance · CPC title

• H03B5/1246

  the means comprising transistors used to provide a variable capacitance · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title