Control systems and methods for power amplifiers operating in envelope tracking mode

Patent metadata

Field	Value
Publication number	US-9287829-B2
Application number	US-201313830555-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Dec 28, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Control systems and methods for power amplifiers operating in envelope tracking mode are presented. A set of corresponding functions and modules are described and various possible system configurations using such functions and modules are presented.

First claim

The invention claimed is:

1. A system for affecting operation of an envelope tracking (ET) amplifier, comprising:
an ET amplifier configured to receive an RF input signal and generate therefrom, an RF output signal based on a response of the ET amplifier, the ET amplifier comprising an amplifier unit wherein the amplifier unit comprises a plurality of stacked transistors operatively coupled to a plurality of bias terminals adapted to receive a set of analog input-control signals;
a set of operating parameters defining the response of the ET amplifier; and
a control circuit adapted to detect an envelope of the RF input signal and generate, based on said envelope signal, the set of analog input-control signals that is provided to the ET amplifier for affecting the response according to the set of operating parameters.

2. The system of claim 1 wherein the plurality of bias terminals comprise a plurality of gate terminals of the plurality of stacked transistors and a drain terminal of an output transistor of the amplifier unit.

3. The system of claim 2 wherein the set of analog input-control signals comprise a plurality of gate-input-control signals and a drain-input-control signal, such as the plurality of gate-input-control signals are provided to the plurality of gate terminals, and the drain-input-control signal is provided to the drain terminal.

4. The system of claim 3 wherein the control circuit further comprises:
an envelope detection circuit adapted to detect the envelope of the RF input signal and generate a corresponding envelope signal;
a waveform generation circuit configured to receive the envelope signal and adapted to generate a set of waveform signals based on the envelope signal and the set of operating parameters, and
an input generation circuit configured to receive the set of waveform signals and adapted to output therefrom the set of analog input-control signals.

5. The system of claim 4 wherein the waveform generation circuit further comprises:
a gate-waveform generation circuit configured to receive the envelope signal and adapted to generate a set of gate-waveform signals based on the envelope signal and the set of operating parameters, and
a drain-waveform generation circuit configured to receive the envelope signal and adapted to generate a drain-waveform signal based on the envelope signal and the set of operating parameters.

6. The system of claim 5 wherein the input generation circuit further comprises:
a gate-input generation circuit configured to receive the set of gate-waveform signals and adapted to generate therefrom the plurality of gate-input-control signals, and
a drain-input generation circuit configured to receive the drain-waveform signal and adapted to generate therefrom the drain-input-control signal.

7. The system of claim 6 wherein the ET amplifier further comprises a variable power supply unit wherein the variable power supply unit is configured to operatively comprise the drain-input generation circuit.

8. The system of claim 7 wherein the drain-input generation circuit is a DC-to-DC converter.

9. The system of claim 8 wherein the DC-to-DC converter is fabricated using one of: a) silicon on sapphire (SOS) technology, and b) silicon on insulator (SOI) technology.

10. The system of claim 7 wherein the amplifier unit further comprises a cascaded series of amplifiers operatively coupled in series, wherein each amplifier unit comprises a plurality of stacked transistors operatively coupled to a plurality of bias terminals adapted to receive the set of analog input-control signals.

11. The system in claim 10 wherein the cascaded series of amplifiers comprises a driver amplifier and a final amplifier, each comprising a drain terminal in correspondence of an output transistor.

12. The system of claim 11 wherein the drain-input generation circuit provides the drain-input-control signal to the driver amplifier and to the final amplifier.

13. The system of claim 12 wherein the drain-input generation circuit provides isolated drain-input-control signals to each of the driver amplifier and the final amplifier.

14. The system of claim 12 further comprising an isolation filter, wherein the isolation filter is inserted within a conduction path between the drain terminal of the driver amplifier and the drain terminal of the final amplifier.

15. The system of claim 14 wherein the isolation filter is configured to pass a DC signal and a signal at a frequency of the envelope signal.

16. The system of claim 14 wherein the isolation filter comprises an inductor in parallel with a capacitor.

17. The system of claim 11 further comprising a second drain-input generation circuit, such as each of the two drain-input generation circuits provides an independent drain-input-control signal to each of the driver amplifier and the final amplifier.

18. The system of claim 17 further comprising a second variable power supply unit comprising the second drain-input generation circuit.

19. The system of claim 10 or claim 11 further comprising a frequency selective filter operatively coupled in series between an output terminal of an amplifier of the cascaded series of amplifiers and an input terminal of a following amplifier.

20. The system of claim 19 wherein the frequency selective filter is configured to attenuate a signal at a frequency of the envelope signal.

21. The system of claim 20 wherein the frequency selective filter is a notch filter.

22. The system of claim 7 further comprising a transceiver unit configured to generate the RF input signal from a baseband data, wherein the combination of the transceiver unit, the variable power supply unit and the amplifier unit is configured to operatively comprise the envelope detection circuit, the gate-waveform generation circuit, the drain-waveform generation circuit, and the gate-input generation circuit.

23. The system of claim 22 wherein the transceiver unit is further configured to operatively comprise at least one of: a) the drain-waveform generation circuit, b) the gate-waveform generation circuit; c) the gate-input generation circuit, and d) the envelope detection circuit.

24. The system of claim 22 wherein the variable power supply unit is further configured to operatively comprise at least one of: a) the drain-waveform generation circuit, b) the gate-waveform generation circuit; c) the gate-input generation circuit, and d) the envelope detection circuit.

25. The system of claim 10 wherein the amplifier unit is further configured to operatively comprise at least one of: a) the drain-waveform generation circuit, b) the gate-waveform generation circuit; c) the gate-input generation circuit, and d) the envelope detection circuit.

26. The system of claim 22 wherein the set of operating parameters further comprises minimizing thermal memory effect of the amplifier unit.

27. The system of claim 22 wherein the waveform generation circuit further comprises circuitry configured to predict a temperature of the amplifier unit based on the RF input signal and provide a correction based on said predicted temperature such as said correction is combined with an output of the waveform generation circuit to further optimize response of the amplifier.

28. The system according to claim 1 wherein the ET amplifier further comprises a temperature detection circuit adapted to provide t

Assignees

• Peregrine Semiconductor Corp

Inventors

• Nobbe Dan William
• Dykstra Jeffrey A
• Olson Chris
• Cable James S

Classifications

• H03F2203/45366

  the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor · CPC title

• H03F1/025

  by using a signal derived from the input signal · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F1/56

  Modifications of input or output impedances, not otherwise provided for · CPC title

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title