Semiconductor device and method for forming the same

Patent metadata

Field	Value
Publication number	US-9972644-B2
Application number	US-201514872156-A
Country	US
Kind code	B2
Filing date	Oct 1, 2015
Priority date	Aug 28, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate;
two source/drain regions disposed on the oxide semiconductor layer;
a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; and
a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; and
a second insulating layer disposed between the oxide semiconductor layer and the source/drain regions, wherein a sidewall of each source/drain region is vertically aligned with a sidewall of the oxide semiconductor layer and a sidewall of the second insulating layer, and the bottom oxide layer directly contacts the sidewall of the source/drain region, the sidewall of the oxide semiconductor layer and the sidewall of the second insulating layer.

2. The semiconductor device according to claim 1 , wherein the second insulating layer comprises an oxide semiconductor material different from that of the oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the second insulating layer has a thickness smaller than that of the oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the second insulating layer and the oxide semiconductor layer comprise indium gallium zinc oxide (InGaZnO), InGaO2, InZnO2, GaInO, ZnInO, or GaZnO.

5. The semiconductor device according to claim 1 , further comprising:
a second gate electrode disposed below the oxide semiconductor layer and overlapped the oxide semiconductor layer.

6. The semiconductor device according to claim 5 , further comprising:
a third insulating layer disposed between the oxide semiconductor layer and the second gate electrode, wherein the third insulating layer comprises a oxide semiconductor material different from the oxide semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises a monolayer structure or a multilayer structure.

8. A semiconductor device, comprising:
a substrate;
an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate;
two source/drain regions disposed on the oxide semiconductor layer;
a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions;
a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer;
a top oxide layer disposed on the high-k dielectric layer, wherein the bottom oxide layer, the high-k dielectric layer and the top oxide layer consists of a sandwiched gate dielectric structure; and
a first gate electrode disposed between the two source/drain regions and on the sandwiched gate dielectric structure, wherein the first gate electrode overlaps the oxide semiconductor layer, and a sidewall of the top oxide layer and the a sidewall of high-k dielectric layer are vertically aligned with a sidewall of the first gate electrode.

9. A semiconductor device, comprising:
a substrate;
an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate;
two source/drain regions disposed on the oxide semiconductor layer;
a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions;
a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer, wherein the bottom oxide layer directly contacts the source/drain regions; and
two via plugs electrically connected to the two source/drain regions respectively, wherein the via plugs contact the bottom oxide layer and do not contact the high-k dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Fu
• Wu Chun-Yuan

Classifications

• H10P14/6519

  the substance being oxygen · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title