Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package

Patent metadata

Field	Value
Publication number	US-9972611-B2
Application number	US-201715475879-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Sep 30, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

First claim

What is claimed is:

1. A stacked semiconductor package, comprising:
a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, the functional silicon die forming a first layer of the stacked semiconductor package;
two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package;
a plurality of Through Silicon Vias (TSVs) formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die at the first layer of the stacked semiconductor package via the WIO2 interface of the functional silicon die;
a test port interface to receive test signals from an external tester and route the test signals through a steering logic communicably interfaced with the two or more memory dies;
wherein the steering logic is to shift data into the two or more memory dies through the plurality of TSVs pursuant to the received test signals from the external tester; and
wherein the steering logic is to further shift the data out of the two or more memory dies as output data and return the output data to the external tester via the test port interface.

2. The stacked semiconductor package of claim 1 :
wherein the test port interface comprises a high speed test interface connected with the external tester, wherein the high speed test interface comprises a plurality of buffers having an I/O speed matching an I/O speed of the two or more memory dies.

3. The stacked semiconductor package of claim 1 :
wherein the steering logic to shift the data out of the two or more memory dies as output data comprises the steering logic to shift the data out of the two or more memory dies pursuant to the received test signals from the external tester without passing the output data through any of the plurality of TSVs; and
wherein the output data is captured as an output signal at the memory layers.

4. The stacked semiconductor package of claim 3 :
wherein the steering logic to return the output data to the external tester via the test port interface comprises the steering logic to return the output signal to the external tester for analysis and comparison to a known good signal.

5. The stacked semiconductor package of claim 1 :
wherein the steering logic to return the output data to the external tester via the test port interface comprises the steering logic to return the output signal to the external tester for analysis to identify a faulty TSV among the plurality of TSVs; and
wherein the steering logic is to further receive a new routing string from the external tester.

6. The stacked semiconductor package of claim 5 :
wherein the test port interface loads the new routing string into the two or more memory dies to bypass the faulty TSV pursuant to instruction signals from the external tester; and
wherein the test port is to receive new test signals from the external tester to repeat a test sequence using the new routing string loaded into the two or more memory dies.

7. The stacked semiconductor package of claim 1 :
wherein the steering logic to shift data into the two or more memory dies through the plurality of TSVs pursuant to the received test signals from the external tester comprises the steering logic to shift data into the two or more memory dies using control signals.

8. The stacked semiconductor package of claim 1 :
wherein the steering logic to shift data into the two or more memory dies through the plurality of TSVs pursuant to the received test signals from the external tester comprises the steering logic to shift data into one of the two memory dies during a first iteration of a test sequence and to shift data into a second one of the two memory dies during a second iteration of the test sequence.

9. The stacked semiconductor package of claim 1 :
wherein the steering logic to shift data into the two or more memory dies through the plurality of TSVs pursuant to the received test signals from the external tester comprises the steering logic shift data into one of the two memory dies and into a specified plurality of cells of the one memory die by uniquely addressing the one memory die pursuant to the received test signals.

10. The stacked semiconductor package of claim 1 :
wherein the steering logic communicably links the test port interface with each of the two or more memory dies through a communications traffic of the functional silicon die.

11. The stacked semiconductor package of claim 1 :
wherein the test port interface is embedded upon the functional silicon die.

12. The stacked semiconductor package of claim 11 :
wherein the test port is co-located with a Double Data Rate (DDR) memory interface of the functional silicon die.

13. The stacked semiconductor package of claim 1 , further comprising:
a plurality of physical memory interfaces electrically interfacing the two or more memory dies to the functional silicon die at the first layer through the memory layers via the plurality of TSVs.

14. The stacked semiconductor package of claim 1 , further comprising:
a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

15. The stacked semiconductor package of claim 1 , wherein the stacked semiconductor package embodies a two-level memory (2LM) stacked die sub-system.

16. The stacked semiconductor package of claim 15 , wherein
the
2LM stacked die sub-system is formed from a first memory die affixed atop a functional silicon die at a bottom layer of the stacked semiconductor package
and
further formed from a second memory die affixed atop the first memory die.

17. The stacked semiconductor package of claim 1 :
wherein a re-routing string computed by the external tester and permanently written to the stacked semiconductor package at a time of manufacture is used to reroute a memory signal path from a defective physical memory interface at an identified defective TSV to a functional signal path traversing a redundant TSV;
wherein the functional silicon die comprises a System On a Chip (SOC) functional silicon die manufactured by the manufacturer of the stacked semiconductor package; and
wherein the re-routing string used to reroute the memory signal path from the defective physical memory interface to the functional signal path is permanently written into a secured fuse block of the SOC functional silicon die at the time of manufacture of the stacked semiconductor package.

18. The stacked semiconductor package of claim 1 :
wherein the first layer is formed from a System On a Chip (SOC) functional silicon die manufactured by the manufacturer of the stacked semiconductor package; and
wherein a second layer is formed from one of a DRAM memory silicon die or a phase change memory die manufactured by a third party and acquired by the manufacturer of the stacked semiconductor package and integrated into the stacked semiconductor package by the manufacturer of the stacked semiconductor package.

19. A method for identifying a faulty Through Silicon Via (TSV) in a stacked semiconductor package, wherein the method comprises:
executing a wake-up sequence on a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, the functional silicon die forming a first layer of the stacked s

Assignees

• Intel Corp

Inventors

• Pappu Lakshminarayana
• Schnarch Baruch
• Nelson Christopher J
• Goldin Schwabova Danka

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W72/01

  Manufacture or treatment · CPC title