Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding

Patent metadata

Field	Value
Publication number	US-9972606-B2
Application number	US-201715604803-A
Country	US
Kind code	B2
Filing date	May 25, 2017
Priority date	Jan 13, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

First claim

What is claimed is:

1. A method of making a chip package, the method comprising:
soldering, to a laminate, a first integrated circuit (IC) chip to which first inner ends of first metal leads, embedded in a first polymer tape, are attached to first peripheral metal pads formed on a first back side of the first IC chip, wherein the first IC chip has a first center portion and a first periphery portion outside the first center portion, wherein the first peripheral metal pads are adjacent to the first back side on the first periphery portion, wherein first central metal pads are adjacent to the first back side on the first center portion, wherein the first IC chip further includes: first solder bumps formed adjacent to a first front side of the first IC chip on the first center portion; and first through silicon vias (TSVs) that extend vertically through the first center portion from the first solder bumps to the first central metal pads, and wherein the first solder bumps attach the first IC chip to the laminate;
bending and bonding first outer ends of the first metal leads, embedded in the first polymer tape, to the laminate;
soldering a second IC chip to the first IC chip, the second IC chip including: second inner ends of second metal leads, embedded in a second polymer tape, that are attached to second peripheral metal pads formed on a second back side of the second IC chip, wherein the second IC chip has a second center portion and a second periphery portion outside the second center portion, wherein the second peripheral metal pads are adjacent to the second back side on the second periphery portion, wherein second central metal pads are adjacent to the second back side on the second center portion, wherein the second IC chip further includes: second solder bumps formed adjacent to a second front side of the second IC chip on the second center portion; and second TSVs that extend vertically through the second center portion from the second solder bumps to the second central metal pads, and wherein the second solder bumps attach the second IC chip to the first IC chip; and
bending and bonding second outer ends of the second metal leads, embedded in the second polymer tape, to the laminate.

2. The method of claim 1 , further comprising:
initially fabricating a first wafer to include at least the first IC chip and the first TSVs; and
initially fabricating a second wafer to include at least the second IC chip and the second TSVs.

3. The method of claim 2 , further comprising:
flipping the first wafer to thin a back side of the first wafer, to expose a back side of each first TSV on which is formed a first central metal pad and forming first peripheral metal pads on a back side of each first IC chip; and
flipping the second wafer to thin a back side of the second wafer, to expose a back side of each second TSV on which is formed a second central metal pad and forming second peripheral metal pads on a back side of each second IC chip.

4. The method of claim 3 , further comprising:
singulating the first IC chip from the first wafer; and
singulating the second IC chips from the second wafer.

5. The method of claim 4 , further comprising:
bonding the first inner ends of the first metal leads, embedded in the first polymer tape, to the first peripheral metal pads on the back side of the first IC chip; and
bonding the second inner ends of the second metal leads, embedded in the second polymer tape, to the second peripheral metal pads on the back side of the second IC chip.

6. The method of claim 1 , wherein the first IC chip and the second IC chip are essentially equal size such that opposing first sidewalls of the first IC chip are vertically aligned with opposing second vertical sidewalls of the second IC chip.

7. A method of making a chip package, the method comprising:
providing a laminate;
attaching a first integrated circuit (IC) chip to the laminate, wherein the first IC chip has a first front side, a first back side opposite the first front side, a first center portion and a first periphery portion outside the first center portion, wherein the first IC chip includes: first solder bumps attached to the first front side, wherein each first solder bump contacts the laminate and a first through-silicon-via (TSV) that extends vertically through the first center portion, wherein first central metal pads are formed adjacent to the first back side on the first center portion and above first TSVs, and wherein first peripheral metal pads are formed adjacent to the first back side on the first periphery portion so as to be physically separated from the first TSVs;
attaching a second integrated circuit (IC) chip to the first IC chip to form a chip stack, wherein the second IC chip has a second front side, a second back side opposite the second front side, a second center portion and a second periphery portion outside the second center portion, wherein the second IC chip includes second solder bumps attached to the second front side, wherein each second solder bump contacts a first central metal pad of the first IC chip and a second through-silicon-via (TSV) that extends vertically through the second center portion of the second IC chip, wherein second central metal pads are formed adjacent to the second back side on the second center portion and above second TSVs, and wherein second peripheral metal pads are formed adjacent to the second back side on the second periphery portion so as to be physically separated from the second TSVs;
bonding first inner ends of first metal leads that are embedded in a first polymer tape to each first peripheral metal pad of the first IC chip and further bonding first outer ends of the first metal leads to the laminate; and
bonding second inner ends of second metal leads that are embedded in a second polymer tape to each second peripheral metal pad of the second IC chip and further bonding second outer ends of the second metal leads to the laminate.

8. The method of claim 7 ,
the first IC chip being flipped such that the first front side corresponds to a first active side upon which the first solder bumps are formed; and
the second IC chip being flipped such that the second front side corresponds to a second active side upon which the second solder bumps are formed.

9. The method of claim 7 , the first solder bumps and the second solder bumps comprising a solder further comprising of any of: tin and lead, lead-free tin alloys yet further comprising any of gold, silver, copper, bismuth, and indium, and conductive epoxies.

10. The method of claim 7 , the laminate comprising a printed circuit board.

11. The method of claim 7 ,
the first metal leads and the second metal leads comprising any of copper, gold, and aluminum; and
the first polymer tape and the second polymer tape comprising one of polyimide and polyamide.

12. The method of claim 7 , the second outer ends of the second metal leads contacting the laminate at a distance from vertical sides of the chip stack greater than that of the first outer ends of the first metal leads contacting the laminate.

13. A method of making a chip package, the method comprising:
providing a laminate; and
attaching a pair of adjacent integrated circuit (IC) chips to the laminate, the pair of adjacent IC chips comprising:
a first IC chip including: first through-silicon-vias (TSVs) that extend vertically through a first center portion of the first IC chip, wherein a first periphery portion surrounds the first center portion; first solder bumps attached to a first front side of the first IC chip, each first solder bump contacting the laminate and a first TSV; and first central metal pa

Assignees

• Globalfoundries Inc

Inventors

• Graf Richard S
• Ventrone Sebastian T

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/701

  Tape-automated bond [TAB] connectors · CPC title