Method of fabricating a gate cap layer

Patent metadata

Field	Value
Publication number	US-9972498-B2
Application number	US-201615081932-A
Country	US
Kind code	B2
Filing date	Mar 27, 2016
Priority date	Dec 7, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

First claim

What is claimed is:

1. A method of fabricating a gate cap layer, comprising:
providing a substrate with an interlayer dielectric disposed thereon;
forming a recess in the interlayer dielectric, filling a metal gate in the lower portion of the recess and exposing an upper portion of the recess;
forming a cap material layer covering the interlayer dielectric and filling in the upper portion of the recess;
forming a first sacrifice layer covering the cap material layer, wherein the first sacrifice layer has a composition different from a composition of the cap material layer;
forming a second sacrifice layer covering the first sacrifice layer, wherein the second sacrifice layer has a composition the same as the composition of the cap material layer;
removing the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric by a chemical mechanical polishing process and using a slurry; and
after the chemical mechanical polishing process, the cap material layer remaining in the upper portion of the recess becoming a gate cap layer.

2. The method of fabricating a gate cap layer of claim 1 , wherein the first sacrifice layer comprises a plurality of sub layers, each of the sub layers comprises a first element and a second element, and the ratio of the second element to the first element in each of the sub layers is variable.

3. The method of fabricating a gate cap layer of claim 1 , wherein besides silicon, the first sacrifice layer comprises a first element the same as the interlayer dielectric comprises.

4. The method of fabricating a gate cap layer of claim 3 , wherein besides silicon, the first sacrifice layer comprises a second element the same as the cap material layer comprises.

5. The method of fabricating a gate cap layer of claim 4 , wherein the first sacrifice layer has a top surface contacting the second sacrifice layer and has a bottom surface contacting the cap material layer, a middle surface of the first sacrifice layer is defined between the top surface and the bottom surface.

6. The method of fabricating a gate cap layer of claim 5 , wherein a ratio of the second element to the first element increases in a direction from the middle surface to the top surface, and increases in a direction from the middle surface to the lower surface.

7. The method of fabricating a gate cap layer of claim 4 , wherein the first element is oxygen and the second element is nitrogen.

8. The method of fabricating a gate cap layer of claim 4 , wherein the first sacrifice layer has a chemical formula of SiO x N y , and 0<X≤2, 0≤Y<4/3.

9. The method of fabricating a gate cap layer of claim 8 , wherein the steps of forming the first sacrifice layer comprises depositing a plurality of sub layers in different chambers, each sub layer formed in each chamber has different ratio of Y to X, and each chamber has different precursor compositions.

10. The method of fabricating a gate cap layer of claim 8 , wherein the steps of forming the first sacrifice layer comprises forming a plurality of sub layers, and each sub layer is formed by performing an oxidation process and a nitridation process to a silicon layer alternately.

11. The method of fabricating a gate cap layer of claim 1 , wherein the first sacrifice layer has a chemical formula of SiO x N y , and X=2, Y=0.

12. The method of fabricating a gate cap layer of claim 1 , wherein a removal rate of the first sacrifice layer is smaller than a removal rate of the second sacrifice layer with respective to the same slurry.

13. The method of fabricating a gate cap layer of claim 1 , wherein the first sacrifice layer does not fill into the recess.

Assignees

• United Microelectronics Corp

Inventors

• Tsai Fu-Shou
• Li Yu-Ting
• Lin Chih-Hsun
• Hsu Li-Chieh
• Liu Yi-Liang
• Huang Po-Cheng
• Li Kun-Ju
• Lin Wen-Chin

Classifications

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P14/6316

  Formation by nitridation, e.g. nitridation of the substrate · CPC title