Selevtive application of interleave based on type of data to be stored in memory

Patent metadata

Field	Value
Publication number	US-9971691-B2
Application number	US-201615263148-A
Country	US
Kind code	B2
Filing date	Sep 12, 2016
Priority date	Sep 12, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of cache memories; and
a cache controller configured to:
allocate a cache entry to store data across the plurality of cache memories, the cache entry including a value in a metadata field indicating an interleave policy; and
selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

2. The apparatus of claim 1 , wherein the interleave policy is configured on a page by page basis for data storage in the plurality of cache memories.

3. The apparatus of claim 1 , wherein the cache controller is further configured to use the value in the metadata field to calculate a cache memory address to be accessed during a cache access transaction.

4. The apparatus of claim 1 , further comprising:
an interleaver circuit configured to use the value in the metadata field to modify a cache memory address to be accessed during a cache access transaction.

5. The apparatus of claim 1 , further comprising:
a plurality of memory controllers; and
a memory controller fabric configured to:
receive a cache access transaction; and
select a memory controller from the plurality of memory controllers to relay the cache access transaction, wherein the memory controller is selected based on the value in the metadata field associated with the cache entry.

6. The apparatus of claim 1 , further comprising:
a memory controller fabric configured to:
receive a cache access transaction; and
relay the cache access transaction to multiple memory controllers,

wherein each of the multiple memory controllers are configured to determine whether to perform the cache access transaction based on the value in the metadata field.

7. The apparatus of claim 1 , further comprising:
a plurality of memory controllers; and
a memory controller fabric configured to:
receive a cache access transaction; and
select a memory controller to relay the cache access transaction based on a memory address of the cache access transaction.

8. The apparatus of claim 1 , further comprising:
a memory controller fabric configured to:
receive a cache access transaction; and
relay the cache access transaction to multiple memory controllers,

wherein the cache controller is configured to use the value in the metadata field to calculate a memory address of the cache access transaction delivered to the memory controller fabric; and
a plurality of memory controllers configured to use the memory address of the cache access transaction to determine whether to perform the cache access transaction.

9. The apparatus of claim 4 , whereby the interleaver circuit is further configured to:
direct data between the cache controller and one or more memory controllers in accordance with the value in the metadata field, thereby maintaining data consistency where a memory controller data bus width is smaller than a cache controller data bus width.

10. The apparatus of claim 1 , wherein:
the metadata field includes a first value to indicate that storage of the data is interleaved between the plurality of cache memories in accordance with a value of a first address bit; and
the metadata field includes a second value to indicate that storage of the data is interleaved between the plurality of cache memories in accordance with a value of a second address bit.

11. The apparatus of claim 10 , wherein:
the data is interleaved between the plurality of cache memories every 128 bytes when the metadata field includes the value of the first address bit; and
the data is interleaved between the plurality of cache memories at an interval greater than 128 bytes when the metadata field includes the value of the second address bit.

12. The apparatus of claim 1 , wherein the data stored across the plurality of cache memories is an operating system (OS) page of data comprising 4096 bytes.

13. The apparatus of claim 1 , wherein the cache controller is configured to infer the metadata value to assign to the cache entry based on heuristics.

14. The apparatus of claim 1 , wherein the cache controller is configured to determine the value in the metadata field to assign to the cache entry based on an identity of a processor entity initiating a memory access transaction that causes the cache entry to be allocated at the cache controller.

15. The apparatus of claim 1 , wherein the cache controller is configured to determine the value in the metadata field to assign to the cache entry based on a number of cache access transactions received to a page of data while servicing a cache miss.

16. The apparatus of claim 1 , wherein the data is stored across the plurality of cache memories in accordance with the interleave policy to enable data access at a desired memory bandwidth.

17. The apparatus of claim 1 , wherein the plurality of cache memories include dynamic random-access memory (DRAM).

18. The apparatus of claim 1 , wherein the interleave policy applied to the cache entry is modified by:
re-shuffling portions of the stored data for the cache entry between the cache memories; and
updating the value in the metadata field to indicate a new interleave policy to be applied when accessing the data from the cache memories.

19. A method for interleaving data storage across a plurality of cache memories, the method comprising:
allocating, at a cache controller in a computer system, a cache entry to store data across the plurality of cache memories in the computer system; and
assigning, at the cache controller in the computer system, a metadata field to the cache entry, wherein the metadata field includes a value to indicate an interleave policy to be selectively applied based on a type of data stored across more than one cache memory in the plurality of cache memories.

20. The method of claim 19 , further comprising: using, at the cache controller in the computer system, the value in the metadata field to calculate a cache memory address to be accessed during a cache access transaction.

21. The method of claim 19 , further comprising: configuring the interleave policy on a page by page basis for data storage in the plurality of cache memories.

22. The method of claim 19 , further comprising: inferring, at the cache controller, the metadata value to assign to the cache entry based on heuristics.

23. The method of claim 19 , further comprising: determining, at the cache controller, the value in the metadata field to assign to the cache entry based on an identity of a processor entity initiating a memory access transaction that causes the cache entry to be allocated at the cache controller.

24. The method of claim 19 , further comprising: determining, at the cache controller, the value in the metadata field to assign to the cache entry based on a number of cache access transactions received to a page of data while servicing a cache miss.

25. The method of claim 19 , further comprising: modifying the interleave policy applied to the cache entry by:
re-shuffling portions of the stored data for the cache entry between the cache memories; and
updating the value in the metadata field to indicate a new interleave policy to be applied when accessing the data from the cache memories.

Assignees

• Intel Corp

Inventors

• Greenspan Daniel
• Fanning Blaise

Classifications

• G06F12/0851 Primary

  Cache with interleaved addressing · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title