Method and device for temperature measurement of FinFET devices

Patent metadata

Field	Value
Publication number	US-9970981-B2
Application number	US-201715648408-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Aug 2, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A semiconductor structure includes a semiconductor device that includes an active region having a semiconductor fin and a gate structure across the semiconductor fin. The gate structure includes a gate electrode. The semiconductor structure also includes a gate line extending from the gate electrode and a metal wiring that is positioned above the gate line and is electrically connected to the gate line through two or more nodes. The semiconductor structure also includes a first measuring electrode and a second measuring electrode coupled respectively to two ends of the metal wiring, the first measuring electrode disposed closer to the gate electrode than the second measuring electrode. The semiconductor structure is configured to measure the temperature of the semiconductor device. During temperature measurement, the first measurement electrode is coupled to a first potential and the second measurement electrode is coupled to a second potential that is lower than the first potential.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor device including an active region having a semiconductor fin and a gate structure across the semiconductor fin, the gate structure including a gate electrode;
a gate line extending from the gate electrode;
a metal wiring that is positioned above the gate line and is electrically connected to the gate line through two or more nodes;
a first measuring electrode and a second measuring electrode coupled respectively to two ends of the metal wiring, the first measuring electrode being disposed closer to the gate electrode than the second measuring electrode;
wherein said semiconductor structure is configured to measure a temperature at the semiconductor device; and
wherein, during temperature measurement, the first measurement electrode is coupled to a first potential and the second measurement electrode is coupled to a second potential that is lower than the first potential.

2. The semiconductor structure of claim 1 , wherein the gate line is connected to the gate electrode and the metal wiring.

3. The semiconductor structure of claim 1 , wherein the metal wiring is a serpentine metal wiring extending along a length thereof and includes a longitudinal portion extending in a direction of the gate line and a lateral portion extending in a direction intersecting the gate line.

4. The semiconductor structure of claim 3 , wherein:
a length of the longitudinal portion of the serpentine metal wiring is greater than a length of the lateral portion so that the longitudinal portion has a resistance greater than that of the lateral portion, and
the first measuring electrode is located at a first end of the serpentine metal wiring close to the gate electrode, and the second measuring electrode is located at a second end of the serpentine metal wiring away from the gate electrode.

5. The semiconductor structure of claim 3 , wherein a length ratio between the longitudinal portion and the lateral portion of the metal wiring is from 10 to 100.

6. The semiconductor structure of claim 3 , wherein a length of the serpentine metal wiring is between 0.1 to 50 microns.

7. The semiconductor structure of claim 1 , wherein the metal wiring comprises a wiring network, the wiring network includes two or more nodes, the nodes electrically connected to the gate line.

8. The semiconductor structure of claim 1 , wherein the semiconductor structure includes one or more gate lines.

9. The semiconductor structure of claim 1 , wherein a total resistance of the metal wiring is in a range of 10 to 10,000 ohms in a temperature range of 25 to 300 degrees Celsius.

10. The semiconductor structure of claim 1 , wherein the metal wiring comprises tungsten or copper.

11. The semiconductor structure of claim 1 , wherein said gate line and said gate electrode are formed from the same layer of conductive material.

12. A method for measuring a temperature of a semiconductor device, the method comprising:
providing a semiconductor device including an active region and a gate structure across a portion of the active region, the gate structure including a gate electrode;
providing a measuring structure that includes:
a gate line extending from the gate electrode;
a metal wiring that is positioned above the gate line and is electrically connected to the gate line through two or more nodes; and
a first measuring electrode and a second measuring electrode coupled respectively to two ends of the metal wiring, the first measuring electrode being disposed closer to the gate electrode than the second measuring electrode;

applying working potentials to a source region and a drain region of the semiconductor device to operate the semiconductor device;
setting a first measurement electrode and a second measurement electrode of the metal wiring to a first potential and a second potential, respectively;
measuring a metal wiring resistance value; and
determining the temperature of the semiconductor device according to the relationship between the metal wiring resistance value and temperature.

13. The method of claim 12 , wherein the first potential is at a working voltage of the gate, and the second potential is a ground potential.

14. The method of claim 12 , wherein the relationship between metal wiring resistance value and temperature is described in a look-up table which lists a plurality of temperatures and corresponding metal wiring resistances.

15. The method of claim 12 , further comprising determining the relationship between the metal wiring resistance value and temperature by:
setting the semiconductor device at different calibration temperatures;
applying a third potential and a fourth potential, respectively, to the first measuring electrode and the second measuring electrode of the metal wiring;
measuring metal wiring resistance values at different temperatures; and
determining the relationship between metal wiring resistance value and temperature.

16. The method of claim 15 , wherein the calibration temperatures are in a range of 25 degrees to 300 degrees Celsius.

17. The method of claim 15 , wherein a difference between the third potential and the fourth potential is in a range from 1 volt to 10 volts.

18. The method of claim 12 , wherein a difference between the first potential and the second potential is in a range from 1 volt to 10 volts.

19. The method of claim 12 , wherein measuring the metal wiring resistance value comprises using a metal voltammetry or four wire Kelvin method.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Feng Junhong
• Gan Zhenghao

Classifications

• H10P72/00

  Handling or holding of wafers, substrates or devices during manufacture or treatment thereof · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H01L21/4853

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic