Augmented capacitor structure for high quality (Q)-factor radio frequency (RF) applications

Patent metadata

Field	Value
Publication number	US-9966426-B2
Application number	US-201514853967-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Sep 14, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

First claim

What is claimed is:

1. An augmented capacitor structure, comprising:
a substrate;
a first capacitor plate, comprising a first conductive layer on the substrate;
an insulator layer on a surface of the first capacitor plate facing away from the substrate;
a second capacitor plate, comprising a second conductive layer on the insulator layer and supported by the first capacitor plate as a first capacitor;
a second capacitor electrically coupled in series with the first capacitor, in which the first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate;
an extended first capacitor structure, comprising a first dummy portion of a third conductive layer and a first dummy via bar, the first dummy via bar directly on at least a first sidewall of the shared first capacitor plate and extending directly along a first surface of the shared first capacitor plate facing the second capacitor plate, the first dummy portion extending along and supported by the first dummy via bar, in which a bottom surface of the first dummy via bar is aligned with a second surface opposite the first surface of the shared first capacitor plate; and
an extended second capacitor structure comprising a second dummy portion of the third conductive layer and a second dummy via bar, the second dummy via bar directly on at least a second sidewall opposite the first sidewall of the shared first capacitor plate and extending directly along the first surface of the shared first capacitor plate, the second dummy portion extending along and supported by the second dummy via bar, in which a bottom surface of the second dummy via bar is aligned with the second surface of the shared first capacitor plate.

2. The augmented capacitor structure of claim 1 , further comprising a third capacitor electrically coupled in series with the second capacitor through a shared active portion of the third conductive layer, in which the first capacitor plate of the third capacitor is separate from the first capacitor plate of the second capacitor.

3. The augmented capacitor structure of claim 2 , further comprising a fourth capacitor electrically coupled in series with the third capacitor, in which the fourth capacitor and the third capacitor share the first capacitor plate of the third capacitor.

4. The augmented capacitor structure of claim 1 , further comprising an active portion of the third conductive layer coupled to the second capacitor plate through a contact via, in which the first dummy portion of the extended first capacitor structure is coplanar with and electrically isolated from the active portion of the third conductive layer.

5. The augmented capacitor structure of claim 1 , further comprising an active portion of the third conductive layer coupled to the second capacitor plate through a first contact via, in which the first dummy via bar of the extended first capacitor structure is adjacent to the second capacitor plate and the first contact via.

6. The augmented capacitor structure of claim 1 , in which the substrate comprises glass, quartz, or silicon.

7. The augmented capacitor structure of claim 1 , incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

8. A method of fabricating an augmented capacitor structure, comprising:
depositing and patterning a first conductive layer on a substrate as a first capacitor plate;
depositing an insulator layer on a surface of the first capacitor plate facing away from the substrate;
depositing and patterning a second conductive layer on the insulator layer as a second capacitor plate of a first capacitor electrically coupled in series with a second capacitor, in which the first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate;
depositing and patterning a third conductive layer as an extended first capacitor structure, including a first dummy portion supported by a first dummy via bar, the first dummy via bar directly on at least a first sidewall of the shared first capacitor plate and extending directly along a first surface of the shared first capacitor plate, the first dummy portion extending along the first dummy via bar, in which a bottom surface of the first dummy via bar is aligned with a second surface opposite the first surface of the shared first capacitor plate; and
depositing and patterning the third conductive layer as an extended second capacitor structure, including a second dummy portion supported by a second dummy via bar, the second dummy via bar directly on at least a second sidewall opposite the first sidewall of the shared first capacitor plate and extending directly along the first surface of the shared first capacitor plate, the second dummy portion extending along the second dummy via bar, in which a bottom surface of the second dummy via bar is aligned with the second surface of the shared first capacitor plate.

9. The method of claim 8 , further comprising depositing and patterning a passivation layer on an interlayer dielectric.

10. The method of claim 8 , further comprising incorporating the augmented capacitor structure into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

11. An augmented capacitor structure, comprising:
a substrate;
a first capacitor plate, comprising a first conductive layer on the substrate;
an insulator layer on a surface of the first capacitor plate facing away from the substrate;
a second capacitor plate, comprising a second conductive layer on the insulator layer and supported by the first capacitor plate as a first capacitor;
a second capacitor electrically coupled in series with the first capacitor, in which the first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate;
an extended first capacitor structure, comprising a first dummy portion of a third conductive layer and a first means for extending directly along a first surface of the shared first capacitor plate facing the second capacitor plate and disposed directly on at least a first sidewall of the shared first capacitor plate, the first dummy portion extending along and supported by the first extending means, in which a bottom surface of the first extending means is aligned with a second surface opposite the first surface of the shared first capacitor plate; and
an extended second capacitor structure, comprising a second dummy portion of the third conductive layer and a second means for extending directly along the first surface of the shared first capacitor plate and disposed directly on at least a second sidewall opposite the first sidewall of the shared first capacitor plate, the second dummy portion extending along and supported by the second extending means, in which a bottom surface of the second extending means is aligned with the second surface of the shared first capacitor plate.

12. The augmented capacitor structure of claim 11 , further comprising a third capacitor electrically coupled in series with the second capacitor through a shared active portion of the third conductive layer, in which the first capacitor plate of the third capacitor is separate from the first capacitor plate of the second capacitor.

13. The augmented capacitor structure of claim 12 , further comprising a fourth capacitor electrically coupled in series with the third capacitor, in which the fou

Assignees

• Qualcomm Inc

Inventors

• Mudakatte Niranjan Sunil
• Kim Daeik Daniel
• Berdy David Francis
• Yun Changhan Hobie
• Lan Je-Hsiung Jeffrey
• Zuo Chengjie
• Velez Mario Francisco
• Mikulka Robert Paul
• Kim Jonghae

Classifications

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title