Silicon-based substrate, semiconductor device, and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9966259-B2
Application number	US-201715585518-A
Country	US
Kind code	B2
Filing date	May 3, 2017
Priority date	May 31, 2013
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×10 14 atoms/cm 3 or more and less than 1×10 19 atoms/cm 3 . Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device, comprising:
fabricating a silicon-based substrate having a first portion provided on a front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, the first impurity concentration being 1×10 14 atoms/cm 3 or more and less than 1×10 19 atoms/cm 3 , and a thickness of the second portion being larger than a thickness of the first portion; and
forming a nitride compound semiconductor layer which is on the front surface of the silicon-based substrate,
wherein a thickness of the first portion is set to be 1 μm or more and 10 μm or less, and
the first impurity concentration is gradually reduced from the second portion toward the surface of the first portion; and
wherein the step of fabricating the silicon-based substrate comprises:
a stage of preparing the silicon-based substrate having the second impurity concentration as a whole; and
a stage of giving a thermal treatment to the silicon-based substrate to outwardly diffuse an impurity in a substrate surface.

2. The method for manufacturing a semiconductor device according to claim 1 ,
wherein the second impurity concentration is set to be 1×10 19 atoms/cm 3 or more and 1×10 20 atoms/cm 3 or less.

3. The method for manufacturing a semiconductor device according to claim 2 ,
wherein the step of fabricating the silicon-based substrate comprises:
a stage of forming a silicon-based semiconductor layer having the first impurity concentration on the silicon-based substrate by epitaxial growth.

4. The method for manufacturing a semiconductor device according to claim 3 ,
wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

5. The method for manufacturing a semiconductor device according to claim 2 ,
wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

6. The method for manufacturing a semiconductor device according to claim 1 ,
wherein the step of fabricating the silicon-based substrate comprises:
a stage of forming a silicon-based semiconductor layer having the first impurity concentration on the silicon-based substrate by epitaxial growth.

7. The method for manufacturing a semiconductor device according to claim 6 ,
wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

8. The method for manufacturing a semiconductor device according to claim 1 ,
wherein, as the impurity, any one or more of boron, phosphorous, aluminum, gallium, arsenic, nitrogen, oxygen, and carbon is used.

Assignees

• Sanken Electric Co Ltd
• Shinetsu Handotai Kk
• Shanken Electric Co Ltd
• Shinetsu Handotai Kk

Inventors

• Shikauchi Hiroshi
• Sato Ken
• Goto Hirokazu
• Shinomiya Masaru
• Tsuchiya Keitaro
• Hagimoto Kazunori

Classifications

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P32/174

  being Group III-V material · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title