Shift register and method for driving the same, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-9965985-B2
Application number	US-201615146089-A
Country	US
Kind code	B2
Filing date	May 4, 2016
Priority date	Sep 25, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

The present disclosure discloses a shift register and a method for driving the same, a gate driving circuit and a display apparatus. The shift register comprises an input module, a reset module, a first control module, a second control module, a first output module and a second output module. With cooperation among the above six modules, the shift register enables the potential at the third node for controlling the first output module to be in a stable state under the function of the first control module and enables the potential at the fourth node for controlling the second output module to be in a stable state under the function of the second control module. In this way, stability of the scanning signal output by the driving signal output end of the shift register is achieved, thereby reducing the noise in the scanning signal output by the driving signal output end, and improving the stability of the output of the shift register.

First claim

I claim:

1. A shift register, comprising:
an input module having a first end connected to an input signal end, a second end connected to a first reference signal end, a third end connected to a first clock signal end, a fourth end connected to a first node, and a fifth end connected to a second node, the input module being configured to provide a signal from the first reference signal end to the first node under the control of the input signal end, and provide a signal from the first clock signal end to the second node under the control of the first reference signal end;
a reset module having a first end connected to a reset signal end, a second end connected to a second reference signal end, a third end connected to a second clock signal end, a fourth end connected to the first node, and a fifth end connected to the second node, the reset module being configured to provide a signal from the second reference signal end to the first node under the control of the reset signal end, and provide a signal from the second clock signal end to the second node under the control of the second reference signal end;
a first control module having a first end connected to a first direct current signal end, a second end connected to a second direct current signal end, a third end connected to the first node, a fourth end connected to a third node, and a fifth end connected to a fourth node, the first control module being configured to provide a signal from the first direct current signal end to the third node under the control of the first node, provide a signal from the second direct current signal end to the third node under the control of the fourth node, and maintain a potential at the third node in a stable state when the third node is in a floating state;
a second control module having a first end connected to the first direct current signal end, a second end connected to the second direct current signal end, a third end connected to the second node, a fourth end connected to the third node, and a fifth end connected to the fourth node, the second control module being configured to provide the signal from the first direct current signal end to the fourth node under the control of the second node, provide the signal from the second direct current signal end to the fourth node under the control of the third node, and maintain a potential at the fourth node in a stable state when the fourth node is in a floating state;
a first output module having a first end connected to a third clock signal end, a second end connected to the third node, and a third end connected to a driving signal output end of the shift register, the first output module being configured to provide a signal from the third clock signal end to the driving signal output end under the control of the third node; and
a second output module having a first end connected to the second direct current signal end, a second end connected to the fourth node, and a third end connected to the driving signal output end, the second output module being configured to provide the signal from the second direct current signal end to the driving signal output end under the control of the fourth node.

2. The shift register according to claim 1 , further comprising: a noise reduction module, having a first end connected to the second direct current signal end, a second end connected to the driving signal output end, and a third end connected to the fourth node, the noise reduction module being configured to provide the signal from the second direct current signal end to the fourth node under the control of the driving signal output end.

3. The shift register according to claim 1 , wherein the input module comprises:
a first switch transistor having a gate connected to the input signal end, a source connected to the first reference signal end, and a drain connected to the first node; and
a second switch transistor having a gate connected to the first reference signal end, a source connected to the first clock signal end, and a drain connected to the second node.

4. The shift register according to claim 1 , wherein the reset module comprises:
a third switch transistor having a gate connected to the reset signal end, a source connected to the first node, and a drain connected to the second reference signal end; and
a fourth switch transistor having a gate connected to the second reference signal end, a source connected to the second node, and a drain connected to the second clock signal end.

5. The shift register according to claim 1 , wherein the first control module comprises:
a fifth switch transistor having a gate connected to the first node, a source connected to the first direct current signal end, and a drain connected to the third node;
a sixth switch transistor having a gate connected to the fourth node, a source connected to the third node, and a drain connected to the second direct current signal end; and
a first capacitor having one end connected to the third node and the other end connected to the second direct current signal end.

6. The shift register according to claim 5 , wherein the first control module further comprises a seventh switch transistor connected between the source of the fifth switch transistor and the first direct current signal end, and
the seventh switch transistor has a gate and a source both connected to the first direct current signal end, and a drain connected to the source of the fifth switch transistor.

7. The shift register according to claim 1 , wherein the second control module comprises:
an eighth switch transistor having a gate connected to the second node, a source connected to the first direct current signal end, and a drain connected to the fourth node;
a ninth switch transistor having a gate connected to the third node, a source connected to the fourth node, and a drain connected to the second direct current signal end; and
a second capacitor having one end connected to the fourth node and the other end connected to the second direct current signal end.

8. The shift register according to claim 1 , wherein the first output module comprises a tenth switch transistor, and the tenth switch transistor has a gate connected to the third node, a source connected to the third clock signal end, and a drain connected to the driving signal output end.

9. The shift register according to claim 8 , wherein the first output module further comprises an eleventh switch transistor connected between the gate of the tenth switch transistor and the third node, wherein the eleventh switch transistor has a gate connected to the first direct current signal end, a source connected to the gate of the tenth switch transistor, and a drain connected to the third node.

10. The shift register according to claim 1 , wherein the second output module comprises a twelfth switch transistor having a gate connected to the fourth node, a source connected to the driving signal output end, and a drain connected to the second direct current signal end.

11. The shift register according to claim 2 , wherein the noise reduction module comprises a thirteenth switch transistor having a gate connected to the driving signal output end, a source connected to the fourth node, and a drain connected to the second direct current signal end.

12. The shift register according to claim 3 , wherein when an active pulse signal for the signal from the input signal end is at a high potential, both the first switch transistor and the second switch transistor are N-type switch transistors; and
when the active pulse signal for the signal from the input signal end is at a low potential, both the first switch transistor and the second switch transistor are P-

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Wang Jiguo

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title