Shift register, gate driving circuit and relevant display device

Patent metadata

Field	Value
Publication number	US-2017200418-A1
Application number	US-201615320613-A
Country	US
Kind code	A1
Filing date	Feb 5, 2016
Priority date	Aug 27, 2015
Publication date	Jul 13, 2017
Grant date	—

Abstract

There are provided a shift register, a gate driving circuit and a relevant display device, comprising a first node controlling module ( 1 ), a second node controlling module ( 2 ), a third node controlling module ( 3 ), a first outputting module ( 4 ) and a second outputting module ( 5 ). The first node controlling module ( 1 ) adjust a potential of a first node (A), the second node controlling module ( 2 ) adjust a potential of a second node (B), the third node controlling module ( 3 ) adjust a potential of a third node (C), the first outputting module ( 4 ) adjust a potential of a driving signal output terminal (Output), and the second outputting module ( 5 ) adjusts the potential of the driving signal output terminal (Output). Through mutual coordination of the five modules, the shift register could control a time length of a scanning signal outputted by the driving signal output terminal (Output) by only changing a time length of an input signal (Input), without changing clock signals (CK,CB) and changing the circuit and process, so that difficulty of the gate driving circuit and complexity of process could be reduced, thereby the cost is reduced.

First claim

1 . A shift register, comprising: a first node controlling module, whose first input terminal is used to receive an input signal, second input terminal is used to receive a first clock signal, third input terminal is used to receive a second clock signal, fourth input terminal is used to receive a first direct current signal, fifth input terminal is connected to a second node, and output terminal is connected to a first node, and configured to provide the input signal to the first node when a potential of the first clock signal is a first potential, provide the first direct current signal to the first node when both a potential of the second clock signal and a potential of the second node are the first potential, and maintain a voltage difference between the third input terminal and the first node to a voltage difference of a previous period of time when the first node is in a floating status;
a second node controlling module, whose first input terminal of is used to receive a second direct current signal, second input terminal is used to receive the first clock signal, third input terminal is used to receive a second clock signal, fourth input terminal is connected to the first node, and output terminal is connected to the second node, and configured to provide the second direct current signal to the second node when a potential of the first clock signal is the first potential, provide the first clock signal to the second node when a potential of the first node is the first potential, and maintain a voltage difference between the third input terminal and the second node to the voltage difference of the previous period of time when the second node is in a floating status; a third node controlling module, whose first input terminal is used to receive the second clock signal, second input terminal is used to receive the first direct current signal, third input terminal is used to receive the second direct current signal, fourth input terminal is connected to the first node, fifth input terminal is connected to the second node, and output terminal is connected to the third node, and configured to provide the first direct current signal to the third node when the potential of the first node is the first potential, provide the second direct current signal to the third node when both the potential of the second clock signal and the potential of the second node are the first potential, and maintain a voltage difference between the second input terminal and the third node to the voltage difference of the previous period of time when the third node is in a floating status; a first outputting module, whose first input terminal is used to receive the second direct current signal, second input terminal is connected to the first node, and output terminal is connected to a driving signal output terminal of the shift register, and configured to provide the second direct current signal to the driving signal output terminal when the potential of the first node is the first potential; a second output module, whose first input terminal is used to receive the first direct current signal, second input terminal is connected to the third node, and output terminal is connected to the driving signal output terminal, and configured to provide the first direct current signal to the driving signal output terminal when the potential of the third node is the first potential.

2 . The shift register according to claim 1 , wherein the first node controlling module comprises; a first switch transistor, a second switch transistor, a third switch transistor, and a first capacitor;
a gate of the first switch transistor is used to receive the first clock signal, a source thereof is used to receive the input signal, and a drain thereof is connected to the first node; a gate of the second switch transistor is connected to the second node, a source thereof is used to receive the first direct current signal, and a drain thereof is connected to a source of the third switch transistor; a gate of the third switch transistor is used to receive the second clock signal, and a drain thereof is connected to the first node; and one terminal of the first capacitor is connected to the first node, and the other terminal thereof is used to receive the second clock signal.

3 . The shift register according to claim 1 , wherein the second node controlling module comprises: a fourth switch transistor, a fifth switch transistor and a second capacitor;
a gate of the fourth switch transistor is connected to the first node, a source thereof is used to receive the first clock signal, and a drain thereof is connected to the second node; a gate of the fifth switch transistor is used to receive the first clock signal, a source thereof is used to receive the second direct current signal, and a drain thereof is connected to the second node; and one terminal of the second capacitor is connected to the second node, and the other terminal thereof is used to receive the second clock signal.

4 . The shift register according to claim 1 , wherein the third node controlling module comprises: a sixth switch transistor, a seventh switch transistor, an eighth switch transistor and a third capacitor;
a gate of the sixth switch transistor is connected to the second node, a source thereof is used to receive the second direct current signal, and a drain thereof is connected to a source of the seventh switch transistor; a gate of the seventh switch transistor is used to receive the second clock signal;
and a drain thereof is connected to the third node;
a gate of the eighth switch transistor is connected to the first node, a source thereof is used to receive the first direct current signal, and a drain thereof is connected to the third node; and
one terminal of the third capacitor is connected to the third node, and the other terminal thereof is used to receive the first direct current signal.

5 . The shift register according to claim 1 , wherein the first outputting module comprises: a ninth switch transistor;
a gate of the ninth switch transistor is connected to the first node, a source thereof is used to receive the second direct current signal, and a drain thereof is connected to the driving signal output terminal.

6 . The shift register according to claim 1 , wherein the second outputting module comprises: a tenth switch transistor;
a gate of the tenth switch transistor is connected to the third node, a source thereof is used to receive the first direct current signal, and a drain thereof is connected to the driving signal output terminal.

7 . The shift register according to claim 1 , wherein when a valid pulse signal of the input signal is a high potential, the first potential is a low potential, and when a potential of the first direct current signal is a high potential, a potential of the second direct current signal is a low potential; or
when the valid pulse signal of the input signal is a low potential, the first potential is a high potential, and when a potential of the first direct current signal is a low potential, a potential of the second direct current signal is a high potential.

8 . The shift register according to claim 2 , wherein when the valid pulse signal of the input signal is a high potential, all of switch transistors are P type transistors; when a valid pulse signal of the input signal is a low potential, all of switch transistors are N type transistors.

9 . The shift register according to claim 8 , wherein when the valid pulse signal of the input signal is a high potential, a rising edge of the input signal aligns with a falling edge of the first clock signal and a rising edge of the second clock signal, and a falling edge of the input signal aligns with a rising edge of th

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Zhang Yi
• Feng Yu
• Zhu Jianchao

Classifications

• G09G2320/064

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• G11C19/287

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• G09G3/3266 Primary

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• G09G2300/0809

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• G09G2310/0286

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