Integrated circuit and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-9960768-B2
Application number	US-201615178154-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Feb 21, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising at least one unit cell, wherein the at least one unit cell comprises:
a first bit circuit configured to process a first bit signal;
a second bit circuit configured to process a second bit signal;
a well spaced apart from boundaries of the at least one unit cell,
wherein the first bit circuit and the second bit circuit share the well, the well comprises a plurality of transistors, the first bit circuit comprises a first transistor from among the plurality of transistors disposed in the well, and the second bit circuit comprises a second transistor from among the plurality of transistors disposed in the well; and
a common circuit configured to receive a control signal and control the first and second bit circuits according to the control signal.

2. The IC of claim 1 , wherein the first bit circuit comprises a first logic gate configured to receive the first bit signal and a signal output from the common circuit, the second bit circuit comprises a second logic gate configured to receive the second bit signal and the signal output from the common circuit, and the first and second logic gates are of a same type.

3. The IC of claim 1 , wherein the first bit circuit comprises a first latch configured to receive the first bit signal and latch the first bit signal according to a signal output from the common circuit, and the second bit circuit comprises a second latch configured to receive the second bit signal and latch the second bit signal according to the signal output from the common circuit.

4. The IC of claim 1 , wherein the first bit circuit comprises a first flip-flop configured to receive the first bit signal and a clock signal, and retain a first output signal output from the first flip-flop according to a signal output from the common circuit and the clock signal, and the second bit circuit comprises a second flip-flop configured to receive the second bit signal and the clock signal, and retain a second output signal output from the second flip-flop according to the signal output from the common circuit and the clock signal.

5. The IC of claim 1 , wherein the at least one unit cell is included in a first block to which a first voltage is selectively applied according to the control signal, and is configured to receive a second voltage from outside of the first block.

6. The IC of claim 5 , wherein signals output from the first and second bit circuits are transmitted to a second block to which the second voltage is applied.

7. A semiconductor device comprising the IC of claim 1 .

8. The IC of claim 1 , wherein the first and second bit circuits have a same configuration.

9. The IC of claim 1 , wherein a layout of the first bit circuit and a layout of the second bit circuit are symmetrical to each other about an axis that crosses the at least one unit cell.

10. The IC of claim 1 , wherein a layout of the first bit circuit corresponds to a layout of the second bit circuit rotated about a point in the at least one unit cell.

11. The IC of claim 1 , wherein each of the first and second bit circuits comprises a level shifter.

12. An integrated circuit (IC) comprising at least one unit cell, wherein the at least one unit cell comprises:
a first bit circuit configured to process a first bit signal;
a second bit circuit configured to process a second bit signal;
a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage;
a second well biased to a second voltage that is different from the first voltage;
a third well biased to the second voltage; and
a common circuit configured to receive a control signal and control the first and second bit circuits according to the control signal,
wherein each of the first and second bit circuits comprises at least one transistor from among a plurality of transistors disposed in the first well,
wherein the second and third wells each contact one side from a pair of sides of the at least one unit cell that face each other, and the pair of sides corresponds to the boundaries of the at least one unit cell,
wherein the common circuit is disposed at the one side from the pair of sides contacted by the second well, and a portion of the second well is disposed in a same area as the common circuit.

13. The IC of claim 12 , further comprising:
a third bit circuit configured to process a third bit signal; and
a fourth bit circuit configured to process a fourth bit signal,
wherein each of the third and fourth bit circuits comprises at least one transistor from among the plurality of transistors disposed in the first well,
wherein the common circuit is configured to control the third and fourth bit circuits according to the control signal.

14. The IC of claim 13 , wherein layouts of the first through fourth bit circuits are respectively disposed in four quadrants of the at least one unit cell.

15. The IC of claim 12 , wherein the first bit circuit comprises a first logic gate configured to receive the first bit signal and a signal output from the common circuit, the second bit circuit comprises a second logic gate configured to receive the second bit signal and the signal output from the common circuit, and the first and second logic gates are of a same type.

16. The IC of claim 12 , wherein the first bit circuit comprises a first latch configured to receive the first bit signal and latch the first bit signal according to a signal output from the common circuit, and the second bit circuit comprises a second latch configured to receive the second bit signal and latch the second bit signal according to the signal output from the common circuit.

17. The IC of claim 12 , wherein the first bit circuit comprises a first flip-flop configured to receive the first bit signal and a clock signal, and retain a first output signal output from the first flip-flop according to a signal output from the common circuit and the clock signal, and the second bit circuit comprises a second flip-flop configured to receive the second bit signal and the clock signal, and retain a second output signal output from the second flip-flop according to the signal output from the common circuit and the clock signal.

18. The IC of claim 12 , wherein the at least one unit cell is included in a first block to which the first voltage is selectively applied according to the control signal, and is configured to receive the second voltage from outside of the first block.

19. The IC of claim 18 , wherein signals output from the first and second bit circuits are transmitted to a second block to which the second voltage is applied.

20. A semiconductor device comprising the IC of claim 12 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dal-Hee
• Seo Jae-Woo
• Park Min-Ho

Classifications

• H03K19/018507

  Interface arrangements · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title