Stacked PA power control

Patent metadata

Field	Value
Publication number	US-9960737-B1
Application number	US-201715451184-A
Country	US
Kind code	B1
Filing date	Mar 6, 2017
Priority date	Mar 6, 2017
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.

First claim

The invention claimed is:

1. A circuital arrangement comprising:
a stack of a plurality of transistors arranged in a cascode configuration, comprising:
(i) an input transistor adapted to receive an input radio frequency (RF) signal; and
(ii) one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor adapted to output, at an adjustable output power, an output RF signal based on the input RF signal;

a first resistor tree comprising a plurality of series connected resistors; and
a low dropout (LDO) regulator coupled to the first resistor tree,
wherein:
the adjustable output power is controlled by varying at least one gate voltage of the one or more cascoded transistors of the stack,
a node of the first resistor tree is configured to provide the at least one gate voltage, and
a control voltage to the LDO regulator varies the at least one gate voltage to provide the adjustable output power from the stack.

2. The circuital arrangement according to claim 1 , further comprising one or more gate capacitors each connected between a gate of a transistor of the one or more cascoded transistors and a reference potential, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with an RF voltage at a drain of the transistor.

3. The circuital arrangement according to claim 2 , wherein the one or more gate capacitors are configured to substantially equalize an RF voltage of the output RF signal at a drain of the output transistor across the plurality of transistors of the stack.

4. The circuital arrangement according to claim 2 , wherein:
the input RF signal is a constant envelope input RF signal, and
the circuital arrangement is adapted to amplify the constant envelope input RF signal and generate the output RF signal as an amplified version of the input RF signal at a drain terminal of the output transistor according to the adjustable output power.

5. The circuital arrangement according to claim 1 , wherein the at least one gate voltage comprises two or more gate voltages of the one or more cascoded transistors.

6. The circuital arrangement according to claim 1 , wherein the at least one gate voltage comprises a gate voltage of the output transistor.

7. The circuital arrangement according to claim 1 , wherein the at least one gate voltage comprises a gate voltage of a transistor of the one or more cascoded transistors that is directly coupled to the input transistor.

8. The circuital arrangement according to claim 1 , further comprising:
a second resistor tree comprising a plurality of series connected resistors,
wherein:
the second resistor tree is configured to provide fixed voltages to remaining gate voltages of the one or more transistors of the cascoded transistors of the stack based on a fixed regulated voltage.

9. A circuital arrangement comprising:
a stack of a plurality of transistors arranged in a cascode configuration, comprising:
(i) an input transistor adapted to receive an input radio frequency (RF) signal; and
(ii) one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor adapted to output, at an adjustable output power, an output RF signal based on the input RF signal; and

a gate voltage control module coupled to gates of the one or more transistors of the stack,
wherein:
the adjustable output power is controlled by varying at least one gate voltage of the one or more cascoded transistors of the stack, and
the gate voltage control module is configured to provide, based on a control voltage, the at least one gate voltage independently from remaining gate voltages of the one or more transistors of the cascoded transistors of the stack.

10. The circuital arrangement according to claim 9 , wherein the gate voltage control module is further configured to provide fixed voltages to remaining gate voltages of the one or more transistors of the cascoded transistors of the stack.

11. The circuital arrangement according to claim 10 , wherein the gate voltage control module further comprises a configuration control module configured to control association of the at least one gate voltage and the fixed voltages to the gates of the one or more transistors of the stack based on configuration control data.

12. The circuital arrangement according to claim 11 , wherein the configuration control module comprises a lookup table adapted to store the configuration control data.

13. The circuital arrangement according to claim 12 , wherein the configuration control data are in correspondence of one or more performance profiles of the circuital arrangement.

14. The circuital arrangement according to claim 12 , wherein the one or more performance profiles comprises: a) a linearity performance, and b) a dynamic range performance.

15. The circuital arrangement according to claim 1 , wherein the plurality of transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

16. The circuital arrangement according to claim 15 , wherein the plurality of transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

17. The circuital arrangement according to claim 1 , wherein the circuital arrangement is adapted to operate as an RF power amplifier for a GSM system.

18. The circuital arrangement according to claim 1 , wherein a supply voltage to the stack is a substantially fixed supply voltage.

19. The circuital arrangement according to claim 18 , wherein the substantially fixed supply voltage is a battery voltage.

20. The circuital arrangement according to claim 1 , wherein a dynamic range of the adjustable output power is larger than 50 dB.

21. The circuital arrangement according to claim 20 , wherein the dynamic range of the adjustable output power is larger than about 60 dB.

22. The circuital arrangement according to claim 1 , wherein:
a supply voltage to the stack is a varying supply voltage, and
a drift of the adjustable output power with respect to the varying supply voltage is compensated for by further varying the at least one gate voltage according to a variable voltage level of the varying supply voltage.

23. A method for controlling an output power of an amplifier arrangement, the method comprising:
providing a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor;
providing a first resistor tree comprising a plurality of series connected resistors and a low dropout (LDO) regulator coupled to the first resistor tree;
supplying a supply voltage across the stack;
providing gate voltages to the one or more cascoded transistors;
inputting a constant envelope radio frequency (RF) signal to the input transistor;
based on the inputting, obtaining an amplified RF signal at the output transistor;
varying at least one gate voltage of the gate voltages to the one or more cascoded transistors; and
based on the varying, controlling the output power of the amplified RF signal,
wherein a node of the first resistor tree is configured to provide the at least one gate voltage, and
wherein a control voltage to the LDO regulator varies the at least one gate voltage for controlling of the output power of the am

Assignees

• Peregrine Semiconductor Croporation
• Psemi Corp

Inventors

• Kovac David

Classifications

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H03F1/0222 Primary

  by using a signal derived from the input signal · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title