ESD transistor for high voltage and ESD protection circuit thereof

Patent metadata

Field	Value
Publication number	US-9431389-B2
Application number	US-201414188136-A
Country	US
Kind code	B2
Filing date	Feb 24, 2014
Priority date	Jun 12, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink region disposed vertically below the collector region, and a buried layer protruding horizontally further than the sink region under the sink region.

First claim

What is claimed is:

1. An ESD transistor, comprising:
a collector region disposed on a surface of a substrate;
a sink region disposed vertically below the collector region;
a buried layer protruding horizontally further than the sink region under the sink region;
an emitter region spaced apart from a base contact region in a base region; and
a first insulating film disposed between the emitter region and the base contact region,
wherein the ESD transistor is a bipolar junction transistor.

2. The ESD transistor of claim 1 , wherein at least two collector regions, base contact regions, sink regions, and buried layers are respectively symmetrically disposed at both sides of the emitter region, and
the at least two buried layers protrude toward the emitter region.

3. The ESD transistor of claim 1 , wherein the sink region has an N-type dopant concentration in a range of 10 19 -10 21 /cm 3 .

4. The ESD transistor of claim 1 , further comprising a collector expansion region disposed under the collector region.

5. The ESD transistor of claim 1 , further comprising:
a second insulating film disposed between the base contact region and the collector region.

6. The ESD transistor of claim 1 , further comprising at least one additional base region surrounding the base region.

7. The ESD transistor of claim 1 , further comprising a tap region spaced apart from the collector region by a third insulating film.

8. The ESD transistor of claim 7 , further comprising an additional well region under the tap region.

9. The ESD transistor of claim 8 , wherein an ESD diode is formed by another well region adjacent to the additional well region therebetween.

10. The ESD transistor of claim 1 , further comprising a resistor connected between an emitter electrode disposed at the upper portion of the emitter region and a base electrode disposed at the upper portion of the base contact region.

11. The ESD transistor of claim 1 , wherein the ESD transistor is configured such that current that is applied to the collector region flows in a U-shaped path toward the emitter region through the base region after passing through the sink region and the buried layer.

12. An ESD transistor, comprising:
a collector region on a surface of a substrate;
a base region on the surface of the substrate;
a base contact region disposed in the base region;
an emitter region spaced apart from the base contact region in the base region; and
a sink region disposed vertically below the collector region and spaced apart from the base region by a well region disposed between the sink region and the base region,
wherein the base region surrounds the emitter region and the base contact region.

13. An ESD protection circuit comprising an ESD transistor that comprises a collector electrode, a base electrode, and an emitter electrode,
wherein the collector electrode is connected to an I/O pad;
the emitter electrode is connected to a ground electrode;
a first resistor is connected between the emitter electrode and the base electrode;
a first diode is connected between the emitter electrode and the collector electrode; and
a charge pump circuit comprising a high-voltage FET that is connected between the collector electrode and the base electrode.

14. The ESD protection circuit of claim 13 , wherein the charge pump circuit comprises a second diode disposed between a collector electrode and a base electrode of the high-voltage FET, and
a second resistor disposed between a base and a ground of the high-voltage FET.

15. The ESD protection circuit of claim 13 , wherein the first diode is grounded at the portion combined with the emitter electrode.

16. The ESD protection circuit of claim 13 , further comprising a core circuit connected in parallel with the ESD transistor,
wherein the first diode is connected in parallel with the ESD transistor and the core circuit.

17. The ESD protection circuit of claim 14 , wherein the first and second diodes are connected in opposite directions to the collector electrode.

18. The ESD protection circuit of claim 13 , wherein the ESD transistor is a bipolar junction transistor.

19. The ESD transistor of claim 12 , wherein the ESD transistor is a bipolar junction transistor.

20. The ESD transistor of claim 12 , further comprising a buried layer disposed below the sink region and protruding horizontally into the well region further than the sink region toward the base region.

21. The ESD transistor of claim 1 , wherein the base region is spaced apart from the sink region.

22. The ESD transistor of claim 1 , wherein the base region is spaced apart from the buried layer.

23. The ESD transistor of claim 1 , wherein the base region contacts a well region disposed between the sink region and the base region.

24. The ESD transistor of claim 1 , wherein at least two buried layers are disposed below the base region and being spaced apart from each other.

25. The ESD transistor of claim 2 , wherein the at least two buried layers are spaced apart from each other.

26. The ESD transistor of claim 12 , further comprising a first buried layer and a second buried layer disposed below the base region, and wherein the first buried layer is spaced apart from the second buried layer.

27. The ESD transistor of claim 26 , wherein at least two well regions are respectively symmetrically disposed at both sides of the emitter region, and the first buried layer contacts one of the at least two well regions, and the second buried layer contacts another of the at least two well regions.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Hwang Kyong Jin
• Shim Jin Seop
• Lee Jae Hyun

Classifications

• H10D62/137

  Collector regions of BJTs · CPC title

• H10D10/40

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title

• H10D10/80

  Heterojunction BJTs · CPC title

• H10D89/711 Primary

  using bipolar transistors as protective elements · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title