Semiconductor heterobarrier electron device and method of making

Patent metadata

Field	Value
Publication number	US-9960249-B2
Application number	US-201514801919-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	May 3, 2012
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method of substantially offsetting polarization charges in an electronic device having a heterobarrier comprising providing a substrate; providing at least one pair of stacks of semiconductor materials; one of the pair of stacks having one or more of spontaneous and piezoelectric polarity where the total polarization charge is opposite to the other of the pair of stacks; whereby due to the opposing polarities, the polarization is balanced and the pair of stacks operate to store electrical energy.

First claim

The invention claimed is:

1. A method of substantially offsetting polarization charges in an electronic device having a heterobarrier comprising the following steps, not necessarily in the following order:
providing a substrate;
providing at least one pair of stacks of semiconductor materials;
one of the pair of stacks having one or more of spontaneous and piezoelectric polarity where the total polarization charge is opposite to the other of the pair of stacks;
whereby due to the opposing polarities, the polarization is balanced and the pair of stacks operate to store electrical energy.

2. The method of claim 1 wherein the electronic device is a varactor.

3. The method of claim 1 wherein the balancing of the polarization substantially eliminates the need for a voltage bias and wherein the at least one pair of stacks are substantially parallel stacks.

4. The method of claim 1 wherein each of at least one pair of stacks comprises at least two layers of a narrow energy gap material surrounding a wide energy gap material, and wherein one of the pair of stacks is N-polar and the other is Ga polar.

5. The method of claim 4 wherein the Ga-polar stack and the N-polar stack comprise two substantially undoped Group III-nitride layers having a barrier layer therebetween and first and second electrical contacts operatively associated with the N-polar and Ga-polar stacks, whereby the N-polar and Ga-polar stacks operate to store electrical energy and the first and second electrical contacts provide for release of the electrical energy.

6. A method of making a semiconductor heterobarrier electronic device comprising the following steps, not necessarily in the following order:
providing a substrate;
providing a pair of stacked layers comprising Group III-nitride semiconductor materials selected from the group of compounds consisting of GaN, InN, AlN, Al x Ga (1-x) N, In x Ga (1-x) N, Al x In (1-x) N, Al x In y Ga (1-x-y) N, where 0<x<1, 0<y<1, and 0<(x+y)<1;
operatively connecting the stacks such that the polarity of one stack opposes the polarity of the other in the pair of stacks; the first of the pair of stacked layers comprising layers that are Group III-polar and the second of the pair comprising layers that are N-polar, the pair of stacked layers being configured such that the spontaneous and/or piezoelectric polarization attributable to the arrangement of the atoms of the materials in first of the pair of stacked layers opposes the spontaneous and/or piezoelectric polarization attributable to the arrangement of the atoms of the materials in the second of pair of stacked layers; the pair of stacked layers being positioned so as to provide electrical energy.

7. The method of claim 6 wherein the first of the pair of stacked layers is spaced apart by a distance in the range of approximately 5 nm to 2 centimeters from the second of the pair of stacked layers; each of the pair of stacked layers ending with a Group III polar surface on one end and an N-polar surface on the opposite end arranged so that the polarities of each of the stacked layers is opposite to the other.

8. The method of claim 6 wherein the step of operatively connecting the pair of stacked layers comprises providing at least one contact configured to connect the pair of stacked layers such that at least one contact interconnects the Group III-polar face of the first of the pair of stacked layers with the N-polar of the second of the pair; and wherein the pair of stacked layers operates to substantially reduce the biasing voltage.

9. The method of claim 6 wherein the device is a heterobarrier varactor; and wherein the first of the pair of the stacked layers has a total polarization that is substantially equal to the total polarization of the second of the pair of stacked layers and wherein each of the stacked layers further comprises a barrier layer therebetween.

10. The method of claim 6 wherein the N-polar and Group III-polar stacked layers each comprises at least two Group III-nitride layers having a barrier layer therebetween; whereby the pair of stacked layers operate to store electrical energy.

11. The method of claim 10 wherein the pair of stacked layers are epitaxially grown on a substrate and wherein the Group III-nitride layers comprise Galium Nitride and wherein the barrier layer comprises AlGaN.

12. The method of claim 11 wherein the Galium Nitride layers are substantially undoped.

13. The device of claim 6 wherein the Group III-N layers are at least approximately 5 nm thick and wherein the barrier layer is a Group III-N layer that is in the range of approximately 3 nm to 40 nm thick depending on exact material composition to minimize strain due to lattice mismatch during growth.

14. The method of claim 6 wherein the total polarization direction of the first of the pair of stacked layers is opposite to the total polarization direction of the second of the pair of stacked layers; and wherein the step of operatively connecting the pair of stacked layers comprises providing at least one contact configured to connect the pair of stacked layers such one of the contacts interconnects the Group III-polar face of the first of the pair of stacked layers with the N-polar of the second of the pair.

15. A method of making an electronic device comprising the following steps, not necessarily in the following order:
providing a substrate;
providing first and second stacks of polar semiconductor materials selected from the group of compounds consisting of GaN, InN, AlN, Al x Ga (1-x) N, In x Ga (1-x) N, Al x In (1-x) N, Al x In y Ga (1-x-y) N, where the values of x and y are greater than zero and less than one and wherein the sum of x and y is less than one, which create a polarization charge by one or more of spontaneous and piezoelectric polarization; the spontaneous and/or piezoelectric polarization charges being attributable to the atomic structure of the semiconductor materials, the first stack being Group III polar and the second stack being N-polar;
the first stack being positioned relative to the second stack such that the total spontaneous and/or piezoelectric polarization charge of the first stack is in a direction opposite to the total spontaneous and/or piezoelectric polarization charge of the second stack.

16. The method of claim 15 wherein the device is one of a varactor, frequency multiplier, pulse shaper, frequency filter, and oscillator; and wherein each stack has a total polarization that is substantially balanced by the total polarization charge of the other stack, and wherein each stack comprises semiconductor layers comprising a narrow energy gap material and a barrier layer comprising a wide energy gap material.

17. The method of claim 15 wherein the first and second stacks are spaced apart from each other and interconnected by at least one electrical connector;
the N-polar and Group III polar stacks each comprising at least two Group III N layers having a barrier layer therebetween;
and wherein the spontaneous polarization is attributable to the arrangement of atoms within the Group III-polar and N-polar layers in a wurtzite crystal lattice structure, the Group III polar surface consisting of Group III-atoms, the N-polar surface consisting of nitrogen atoms, and wherein the piezoelectric polarization is attributable to the differences in atom spacing within lattices of different Group III-N semiconductor layers;
whereby the N-polar and Group III polar stacks operate to store electrical energy and the at least one electrical connector provides for release of the electrical energy.

Assignees

• U S Army Res Laboratory Attn Rdrl Loc I
• Us Army

Inventors

• Shah Pankaj B

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/93

  Electricity · mapped topic

• H01L21/0254

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic