Semiconductor device including a LDMOS transistor

Patent metadata

Field	Value
Publication number	US-9960229-B2
Application number	US-201615191854-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface;
at least one LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate; and
a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with a body contact region of the LDMOS transistor,
wherein the doped buried layer is self-depleting and source grounded, the dope buried layer spaced from a channel region by a portion of the semiconductor substrate,
wherein the substrate, the channel layer and the doped buried layer are doped with a first conductivity type and the dopant concentration of the buried layer is greater than a dopant concentration of the substrate and less than a dopant concentration of the channel region.

2. The semiconductor device of claim 1 , wherein the doped buried layer extends continuously throughout a lateral area of the semiconductor substrate.

3. The semiconductor device of claim 1 , wherein the doped buried layer extends continuously under a source region, a gate and a drain region of the LDMOS transistor.

4. The semiconductor device of claim 1 , wherein the body contact region is doped with the first conductivity type and has a dopant concentration greater than the dopant concentration of the channel region.

5. The semiconductor device of claim 1 , wherein the RESURF structure further comprises a lightly doped region extending from a gate towards a drain region of the LDMOS transistor.

6. The semiconductor device of claim 1 , wherein the RESURF structure further comprises at least one field plate.

7. The semiconductor device of claim 1 , wherein RESURF structure is dimensioned such that an electric field at the front surface in a region between a gate and a drain region is less than 0.5 MV/cm.

8. The semiconductor device of claim 1 , further comprising a field plate having a length, L FP , of 0.8 μm to 1.2 μm from a drain-sided edge of a gate and a gate-sided edge of a drain and a height, D FP , of 0.1 μm to 0.2 μm above a drift zone, wherein the gate has a length, L G , of 0.2 μm to 0.5 μm, the drift zone has a length, L LDD , of 2.5 μm to 3.2 μm from a drain-sided edge of the gate to a gate-sided edge of a drain metal contact, and a depth, D LDD , of 0.1 μm to 0.5 μm from the front surface and the doped buried layer has a depth, D, of 0.5 μm to 2.5 μm from the front surface.

9. The semiconductor device of claim 1 , further comprising a field plate having a length, L FP , of 0.4 μm to 1.0 μm from a drain-sided edge of a gate and a gate-sided edge of a drain and a height, D FP , of 0.05 μm to 0.15 μm above a drift zone, wherein the gate has a length, L G , of 0.15 μm to 0.3 μm, the drift zone has a length, L LDD , of 0.8 μm to 2.5 μm from a drain-sided edge of the gate to a gate-sided edge of a drain metal contact, and a depth, D LDD , of 0.1 μm to 0.5 μm from the front surface and the doped buried layer has a depth, D, of 0.3 μm to 2.0 μm from the front surface.

10. The semiconductor device of claim 1 , further comprising a field plate having a length, L FP , of 0.8 μm to 2.0 μm from a drain-sided edge of a gate and a gate-sided edge of a drain and a height, D FP , of 0.15 μm to 0.35 μm above a drift zone, wherein the gate has a length, L G , of 0.3 μm to 0.8 μm, the drift zone has a length, L LDD , of 3.0 μm to 8.0 μm from a drain-sided edge of the gate to a gate-sided edge of a drain metal contact, and a depth, D LLD , of 0.1 μm to 1.0 μm from the front surface and the doped buried layer has a depth, D, of 0.5 μm to 3.0 μm from the front surface.

11. The semiconductor device of claim 1 , wherein the semiconductor device has a breakdown voltage of at least 60 volts while supporting a saturation current of at least 0.15 A/mm.

12. The semiconductor device of claim 1 , further comprising a conductive via extending from the front surface to the rear surface of the substrate.

13. The semiconductor device of claim 12 , wherein the conductive via is coupled to a source region of the LDMOS transistor.

14. The semiconductor device of claim 12 , wherein the conductive via extends through the body contact region.

15. The semiconductor device of claim 12 , wherein the conductive via includes a first conductive portion adjacent the rear surface which fills the via and a second conductive portion arranged on the first portion which lines side walls of the via and surrounds a gap.

16. A method, comprising:
implanting a self-depleting layer with a dopant concentration of a first conductivity type within a semiconductor substrate comprising a bulk resistivity ρ≥100 Ohm.cm; and
forming an LDMOS transistor in a front surface of the substrate, such that a source region, a channel region, a drift region and a drain region are spaced apart from the self-depleting layer by a portion of the substrate, wherein the body contact region extends to, and is coupled with, the self-depleting layer, wherein the portion of the substrate is positioned in a vertical direction between the self-depleting layer and the source, channel and drain regions.

17. The method of claim 16 , wherein the self-depleting layer extends continuously throughout a lateral area of the substrate.

18. The method of claim 16 , wherein the substrate, the channel layer and the self-depleting layer are doped with a first conductivity type and the dopant concentration of the self-depleting layer is greater than a dopant concentration of the substrate and less than a doping concentration of the channel region.

19. The method of claim 18 , wherein the body contact region is doped with the first conductivity type and has a dopant concentration greater than the dopant concentration of the channel region.

20. The method of claim 16 , further comprising: inserting a via into the front surface of the substrate such that the body contact region surrounds the via;
inserting conductive material into the via; and
electrically coupling the conductive material to the source region.

21. The method of claim 20 , wherein inserting the conductive material into the via comprises inserting conductive material into the via so as to form a first portion at a base of the via which fills the via and inserting conductive material into an upper portion of the via which lines side walls of the via so as to form a second portion which surrounds a gap.

22. The method of claim 20 , further comprising:
removing a portion of the rear surface of the substrate to expose the conductive material within the via at the rear surface; and
applying a conductive layer to the rear surface and the conductive material.

23. A semiconductor device, comprising:
a semiconductor substrate having a bulk resistivity ρ≥100 Ohm.cm, a front surface and a rear surface;
at least one LDMOS transistor in the semiconductor substrate, the LDMOS transistor comprising a source region, a drain region, a channel region, a drift region and a body contact region, wherein the source region is coupled to a conductive layer on the rear surface of the substrate;
a doped buried layer arranged in the substrate, spaced at a distance from the front surface and the rear surface, and coupled with the body contact region of the LDMOS transistor;
a gate shield extending from a gate towards the source region of the LDMOS transistor; and
a field plate extending

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias
• Braun Michaela
• Eckl Christian

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H03F1/0288

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title