Metal bond pad with cobalt interconnect layer and solder thereon

Patent metadata

Field	Value
Publication number	US-9960135-B2
Application number	US-201514665799-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Mar 23, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

First claim

The invention claimed is:

1. A method of forming an integrated circuit, comprising:
providing a substrate including at least one integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads coupled to circuit nodes on said IC device, said plurality of bond pads including a metal bond pad area;
depositing a cobalt comprising connection layer directly on said metal bond pad area;
patterning said cobalt comprising connection layer to provide a cobalt bond pad surface on said plurality of bond pads; and
forming a solder material directly on said cobalt bond pad surface of the cobalt comprising connection layer to form a three layer stack of the solder material directly on the cobalt comprising connection layer directly on the oxidizable uppermost metal interconnect layer.

2. The method of claim 1 , wherein said providing said substrate further includes at least one patterned passivation layer defining a trench including dielectric sidewalls above said metal bond pad area, and wherein said cobalt comprising connection layer extends directly over said dielectric sidewalls onto said passivation layer to completely cap said metal bond pad area.

3. The method of claim 1 , wherein said depositing comprises sputtering, further comprising before said sputtering removing native oxide on a surface of said uppermost metal interconnect layer using a sputter etch comprising method.

4. The method of claim 1 , wherein said uppermost metal interconnect layer comprises primarily aluminum by weight.

5. The method of claim 1 , wherein said solder material comprises a solder ball that comprises Sn and Ag.

6. The method of claim 1 , wherein said uppermost metal interconnect layer comprises primarily copper by weight, titanium, or a titanium compound material.

7. The method of claim 1 , wherein said patterning said cobalt comprising connection layer comprises patterning a photoresist layer on said cobalt comprising connection layer, and then wet etching said cobalt comprising connection layer.

8. The method of claim 1 , wherein said cobalt comprising connection layer comprises at least one non-cobalt transition metal in a concentration from 2 wt. % to 60 wt. %.

9. The method of claim 1 , wherein a thickness of said cobalt comprising connection layer is between 100 Angstroms and 2 μm thick.

10. The method of claim 1 , wherein said cobalt comprising connection layer includes at least 99% cobalt by weight.

11. A method of forming an integrated circuit, comprising:
providing a substrate including at least one integrated circuit (IC) device formed thereon having an uppermost metal interconnect layer which provides a plurality of bond pads coupled to circuit nodes on said IC device, said plurality of bond pads including a metal bond pad area comprising primarily aluminum;
depositing a cobalt comprising connection layer directly on said aluminum metal bond pad area;
patterning said cobalt comprising connection layer to provide a cobalt bond pad surface on said plurality of bond pads; and
forming a solder ball directly on the cobalt bond pad surface of the cobalt comprising connection layer to form a three layer stack of the solder ball directly on the cobalt comprising connection layer which is directly on the aluminum of the uppermost metal interconnect layer, wherein the solder ball comprises Sn and Ag.

12. The method of claim 11 , wherein said providing said substrate further includes at least one patterned passivation layer defining a trench including dielectric sidewalls above said metal bond pad area, and wherein said cobalt comprising connection layer extends directly over said dielectric sidewalls onto said passivation layer to completely cap said metal bond pad area.

13. The method of claim 11 , wherein said depositing comprises sputtering, further comprising before said sputtering removing native oxide on a surface of said uppermost metal interconnect layer using a sputter etch comprising method.

14. The method of claim 11 , wherein said patterning said cobalt comprising connection layer comprises patterning a photoresist layer on said cobalt comprising connection layer, and then wet etching said cobalt comprising connection layer.

15. The method of claim 11 , wherein said cobalt comprising connection layer comprises at least one non-cobalt transition metal in a concentration from 2 wt. % to 60 wt. %.

16. The method of claim 11 , wherein a thickness of said cobalt comprising connection layer is between 100 Angstroms and 2 μm thick.

17. The method of claim 11 , wherein said cobalt comprising connection layer includes at least 99% cobalt by weight.

Assignees

• Texas Instruments Inc

Inventors

• Rinck Helmut
• Bauer Gernot
• Zrile Robert
• Schachtschneider Kai-Alexander
• Otte Michael
• Wiesner Harald

Classifications

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01257

  by reflowing · CPC title

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title