Semiconductor device and manufacturing method thereof

US9960116B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9960116-B2
Application numberUS-56360809-A
CountryUS
Kind codeB2
Filing dateSep 21, 2009
Priority dateSep 25, 2008
Publication dateMay 1, 2018
Grant dateMay 1, 2018

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resistor unit is electrically disconnected as necessary. The first resistor units may be either a unit including a single resistor or may be a unit including a plurality of resistors.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer, each provided in a first direction; and a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, each provided in a second direction orthogonal to the first direction, wherein a part of the first metal layer is connected to one end of the first resistor, the other end of the first resistor is connected to a first part of the second metal layer, a second part of the second metal layer is connected to one end of the second resistor, the other end of the second resistor is connected to a first part of the third metal layer, a second part of the third metal layer is connected to one end of the third resistor, the other end of the third resistor is connected to a first part of the fourth metal layer, a second part of the fourth metal layer is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to a first part of the fifth metal layer, a second part of the fifth metal layer is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to a third part of the third metal layer. 2. The semiconductor device according to claim 1 , wherein an impurity in the first to fifth resistors is selected from the group of phosphorus, arsenic and boron. 3. The semiconductor device according to claim 1 , wherein the first to fifth resistors have lower crystallinity than the first to fifth metal layers. 4. The semiconductor device according to claim 1 , wherein a resistivity of the first to fifth resistors is 100 times or more than a resistivity of the first to fifth metal layers. 5. The semiconductor device according to claim 1 , wherein a portion of the third metal layer is configured to be disconnected. 6. A semiconductor device comprising: a substrate; a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer over the substrate, each provided in a first direction; and a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, each provided in a second direction orthogonal to the first direction, wherein a part of the first metal layer is connected to one end of the first resistor, the other end of the first resistor is connected to a first part of the second metal layer, a second part of the second metal layer is connected to one end of the second resistor, the other end of the second resistor is connected to a first part of the third metal layer, a second part of the third metal layer is connected to one end of the third resistor, the other end of the third resistor is connected to a first part of the fourth metal layer, a second part of the fourth metal layer is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to a first part of the fifth metal layer, a second part of the fifth metal layer is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to a third part of the third metal layer, and wherein the substrate is selected from the group of a glass substrate, a quartz substrate, a resin substrate, and a metal substrate. 7. The semiconductor device according to claim 6 , wherein the first to fifth resistors have lower crystallinity than the first to fifth metal layers. 8. The semiconductor device according to claim 6 , wherein a resistivity off the first to fifth resistors is 100 times or more than a resistivity of the first to fifth metal layers. 9. The semiconductor device according to claim 6 , wherein a portion of the third metal layer is configured to be disconnected.

Assignees

Inventors

Classifications

  • changeable by the use of an external beam, e.g. laser beam or ion beam · CPC title

  • H10W20/498Primary

    Resistive arrangements or effects of, or between, wiring layers · CPC title

  • Resistor networks not otherwise provided for · CPC title

  • Structural combinations of resistors · CPC title

  • Electricity · mapped topic

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What does patent US9960116B2 cover?
A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first resistor units which is connected serially to each other and a second resistor unit which is connected in parallel to part of the first resistor units. Then, after the measurement of a semiconductor integrated circuit, the second resisto…
Who is the assignee on this patent?
Ohshima Kazuaki, Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10W20/498. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).