Method for making a structural capacitor

US9959974B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9959974-B2
Application numberUS-201514633616-A
CountryUS
Kind codeB2
Filing dateFeb 27, 2015
Priority dateFeb 27, 2015
Publication dateMay 1, 2018
Grant dateMay 1, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A structural capacitor having a plurality of planar dielectric layers and a plurality of positive and negative electrodes with the positive and negative electrodes alternating between each dielectric layer and methods for making structural capacitors are provided. First and second spaced apart holes are provided through each dielectric layer as well as the electrodes so that the first holes in the electrodes register with the first holes in the dielectric layer and likewise for the second holes. The capacitor is formed by stacking the dielectric layers and electrodes on two spaced apart alignment pins with a positive alignment pin extending through the first holes and a negative alignment pin extending through the second holes in the dielectric layers and electrodes. These alignment pins maintain layer alignment during subsequent thermal and pressure processing to bond together the dielectric and electrode layers into an integral structural material. After processing, the alignment pins are removed and replaced with electrode pins, where the positive electrode pin is in electrical contact only with the positive electrodes and the negative electrode pin is in electrical contact only with the negative electrodes. The electrode pins are used for subsequent electrical and mechanical connectorization to the structural capacitor.

First claim

Opening claim text (preview).

We claim: 1. A method of constructing a structural capacitor comprising the steps of: forming a plurality of dielectric layers, each layer having a first and a second spaced apart alignment holes extending between a top and a bottom of each dielectric layer, forming a plurality of planar electrically conductive positive and negative electrodes, each electrode having a first and a second spaced apart alignment holes extending between a top and a bottom of each electrode, said positive electrodes having an electrically conductive portion in electrical contact with said first hole but not said second hole and said negative electrodes having an electrically conductive portion in electrical contact with said second hole but not said first hole, arranging a positive alignment pin and a negative alignment pin in a spaced apart and parallel relationship, creating a stack having a plurality of dielectric layers and alternating positive and negative electrodes stacked upon each other so that said positive alignment pin extends through said first holes in said dielectric layers and electrodes and so that said negative alignment pin extends through said second holes in said dielectric layers and electrodes, and removing the structural capacitor from the top plate, bottom plate, and alignment pins, and then placing electrically conductive electrode pins into said first and second alignment holes alignment holes. 2. The method as defined in claim 1 and comprising the step of sandwiching said stack between a top plate and a bottom plate. 3. The method as defined in claim 1 wherein said dielectric layers each comprise a fiber reinforced polymer. 4. The method as defined in claim 3 wherein said polymer comprises an epoxy polymer. 5. The structural capacitor as defined in claim 3 wherein said fiber comprises an interwoven mesh. 6. The method as defined in claim 3 wherein said fiber comprises a glass fiber. 7. The method as defined in claim 1 further comprising the step of placing an electrically conductive fill material in said first and second alignment holes. 8. The method as defined in claim 7 wherein said fill material fills a space between said electrode pins and said stack. 9. A method of constructing a structural capacitor comprising the steps of: forming a plurality of dielectric layers, each layer having a first and a second spaced apart alignment holes extending between a top and a bottom of each dielectric layer, forming a plurality of planar electrically conductive positive and negative electrodes, each electrode having a first and a second spaced apart alignment holes extending between a top and a bottom of each electrode, said positive electrodes having an electrically conductive portion in electrical contact with said first hole but not said second hole and said negative electrodes having an electrically conductive portion in electrical contact with said second hole but not said first hole, arranging a positive alignment pin and a negative alignment pin in a spaced apart and parallel relationship, creating a stack having a plurality of dielectric layers and alternating positive and negative electrodes stacked upon each other so that said positive alignment pin extends through said first holes in said dielectric layers and electrodes and so that said negative alignment pin extends through said second holes in said dielectric layers and electrodes, and removing the structural capacitor from the top plate, bottom plate, and alignment pins, and then placing electrically conductive electrode pins into said first and second alignment holes alignment holes.

Assignees

Inventors

Classifications

  • of synthetic material, e.g. derivatives of cellulose (H01G4/16 takes precedence) · CPC title

  • of fibrous material, e.g. paper · CPC title

  • Fibrous material or synthetic material · CPC title

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

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Frequently asked questions

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What does patent US9959974B2 cover?
A structural capacitor having a plurality of planar dielectric layers and a plurality of positive and negative electrodes with the positive and negative electrodes alternating between each dielectric layer and methods for making structural capacitors are provided. First and second spaced apart holes are provided through each dielectric layer as well as the electrodes so that the first holes in …
Who is the assignee on this patent?
U S Army Res Laboratory Attn Rdrl Loc I, Us Army
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).