Non-volatile memory device having multiple string select lines

Patent metadata

Field	Value
Publication number	US-2016372202-A1
Application number	US-201514742054-A
Country	US
Kind code	A1
Filing date	Jun 17, 2015
Priority date	Jun 17, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

First claim

1 . An apparatus for controlling a non-volatile memory device, the apparatus comprising:
a 3D array of nonvolatile memory cells, the 3D array including:
a plurality of layers, each layer comprising (1) a plurality of NAND strings of nonvolatile memory cells, each of plurality of NAND strings coupled to a bit line and (2) a plurality of string select lines (SSL) and one or more word lines, the plurality of SSLs and the one or more word lines arranged orthogonally to the plurality of NAND strings,
the one more word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of stacks and the one or more word lines,
each of the plurality of NAND strings further comprising a plurality of string-select-line (SSL) transistors coupling the SSLs to the NAND strings,
a first SSL transistor and a second SSL transistor forming a SSL string adjacent to a second SSL string comprised of an SSL transistor sharing a bias condition with the first SSL transistor and another SSL transistor sharing a bias condition with the second SSL transistor and repeated every four bit lines,
wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive a second voltage, and wherein the second SSL being nearer to the one or more word lines.

2 . The apparatus according to claim 1 , further comprising:
a control circuit configured to inhibit programming cells sharing a word line and not sharing a bit line, the bit lines having a different bias, by applying a first voltage to the first SSL and a second voltage to the second SSL, the second SSL being nearer to the word line, and the first voltage being 0 voltage and the second voltage being lower than the VDD voltage and greater than 0.

3 . The apparatus according to claim 1 , further comprising:
a control circuit configured to inhibit programming cells sharing a word line and sharing the bitline, the bit line being VDD, by applying a first voltage to the first SSL transistor and a second voltage to the second SSL, the second SSL being nearer to the word line, and the first voltage being VDD voltage and the second voltage being lower than the VDD voltage and greater than 0

4 . The apparatus according to claim 1 , further comprising:
a control circuit configured to inhibit programming cells sharing a word line and sharing the bitline, the bit line being 0, by applying a first voltage to the first SSL transistor and a second voltage to the second SSL, the second SSL being nearer to the word line, and the first voltage being 0 voltage and the second voltage being lower than the VDD voltage and greater than 0.

5 . The apparatus according to claim 1 , wherein the non-volatile memory device is a vertical channel-type three-dimensional semiconductor memory device comprising a substrate and a plurality of through-holes.

6 . The apparatus according to claim 5 , wherein each of the plurality of NAND strings of nonvolatile memory cells memory cells being associated with an even bit line or an odd bit line, and each of the plurality of NAND strings associated with the even bit line can be programmed independent of the plurality of NAND strings associated with the odd bit line.

7 . The apparatus according claim 1 , wherein the non-volatile memory device comprises a flash memory.

8 . The apparatus according claim 1 , wherein the non-volatile memory device comprises a NAND flash memory.

9 . The apparatus according claim 1 , further comprising: a 3D NAND device comprising at least one of an n-type doped substrate formed by n-type dopant implantation, a p-type doped substrate, or an undoped substrate.

10 . A non-volatile memory device:
a 3D array of nonvolatile memory cells, the 3D array including:
a plurality of layers, each layer comprising (1) a plurality of NAND strings of nonvolatile memory cells, each of plurality of NAND strings coupled to a bit line and (2) a plurality of string select lines (SSL) and one or more word lines, the plurality of SSLs and the one or more word lines arranged orthogonally to the plurality of NAND strings,
the one more word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of stacks and the one or more word lines,
each of the plurality of NAND strings further comprising a plurality of string-select-line (SSL) transistors coupling the SSLs to the NAND strings,
a first SSL transistor and a second SSL transistor forming a SSL string adjacent to a second SSL string comprised of an SSL transistor sharing a bias condition with the first SSL transistor and another SSL transistor sharing a bias condition with the second SSL transistor and repeated every four bit lines,
wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive a second voltage, and wherein the second SSL being nearer to the one or more word lines.

11 . The nonvolatile memory device of claim 10 , further comprising:
a control circuit configured to inhibit programming cells sharing a word line and not sharing a bit line, the bit lines having a different bias, by applying a first voltage to the first SSL and a second voltage to the second SSL, the second SSL being nearer to the word line, and the first voltage being 0 voltage and the second voltage being lower than the VDD voltage and greater than 0.

12 . The nonvolatile memory device of claim 10 , further comprising:
a control circuit configured to inhibit programming cells sharing a word line and sharing the bitline, the bit line being VDD, by applying a first voltage to the first SSL transistor and a second voltage to the second SSL, the second SSL being nearer to the word line, and the first voltage being VDD voltage and the second voltage being lower than the VDD voltage and greater than 0

13 . The nonvolatile memory device of claim 10 , further comprising:
a control circuit configured inhibit programming cells sharing a word line and sharing the bitline, the bit line being 0, by applying a first voltage to the first SSL transistor and a second voltage to the second SSL, the second SSL being nearer to the word line, and the first voltage being 0 voltage and the second voltage being lower than the VDD voltage and greater than 0.

14 . The nonvolatile memory device of claim 10 , wherein the non-volatile memory device is a vertical channel-type three-dimensional semiconductor memory device comprising a substrate and a plurality of through-holes.

15 . The nonvolatile memory device of claim 10 , wherein each of the plurality of NAND strings of nonvolatile memory cells memory cells being associated with an even bit line or an odd bit line, and each of the plurality of NAND strings associated with the even bit line can be programmed independent of the plurality of NAND strings associated with the odd bit line.

16 . The nonvolatile memory device of claim 10 , wherein the nonvolatile memory device comprises a flash memory.

17 . The nonvolatile memory device of claim 10 , wherein the nonvolatile memory device comprises a NAND flash memory.

18 . The nonvolatile memory device of claim 10 , further comprising: a 3D NAND device comprising at least one of an n-type doped substrate formed by n-type dopant implantation, a p-type doped substrate, or an undoped substrate.

19 . A method for controlling a nonvolatile memory device, the method comprising:
providing a nonvolatile memory device that includes a 3D array of nonvolatile memory cells, the 3D array including:
a plurality of layer

Assignees

• Macronix Int Co Ltd

Inventors

• Suzuki Atsuhiro
• Lee Chih-Wei
• Ku Shaw-Hung

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title