Memory system including non-volatile memory of which access speed is electrically controlled

Patent metadata

Field	Value
Publication number	US-9959919-B2
Application number	US-201615067723-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Mar 20, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.

First claim

The invention claimed is:

1. A memory system comprising:
a non-volatile memory of which access speed is electrically controlled;
first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory; and
second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
wherein the first circuitry selects the first region on the basis of at least one of a frequency of access, and an access history.

2. The memory system according to claim 1 ,
wherein the first circuitry selects, as the first region, a region closer to a processor than the second region, in the memory region of the non-volatile memory.

3. The memory system according to claim 1 ,
wherein the first circuitry permits that plurality of processors access a common first region.

4. The memory system according to claim 1 , further comprising:
a first storage that is provided separately from the non-volatile memory and stores at least one of data stored in the non-volatile memory and data to be stored in the non-volatile memory.

5. The memory system according to claim 4 ,
wherein the first storage comprises one or more levels of cache memories.

6. The memory system according to claim 4 ,
wherein the first storage comprises a main memory of the processor, and
the non-volatile memory stores at least one of data stored in the main memory and data to be stored in the main memory.

7. The memory system according to claim 1 ,
wherein the non-volatile memory is a magnetoresistive random access memory (MRAM).

8. A memory system comprising:
a non-volatile memory of which access speed is electrically controlled;
first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory; and
second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
wherein the first circuitry selects the first region on the basis of at least one of a latency of a processor, an endurance of the non-volatile memory, a frequency of access, and an access history,
wherein the second circuitry changes the access speed of the first region from a first speed to a second speed faster than the first speed, and after a predetermined period of time elapses, returns the access speed of the first region from the second speed to the first speed.

9. A memory system comprising:
a non-volatile memory of which access speed is electrically controlled;
first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory; and
second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
wherein the first circuitry selects the first region on the basis of at least one of a latency of a processor, an endurance of the non-volatile memory, a frequency of access, and an access history,
wherein the first regions is closer to a processor than the second region.

10. A memory system comprising:
a non-volatile memory of which access speed is electrically controlled;
first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory; and
second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
wherein the first region comprises a plurality of sub-regions, and
the second circuitry adjusts such that the access speeds of the plurality of sub-regions are different from one another.

11. The memory system according to claim 10 ,
wherein the distances of the plurality of sub-regions from the processor are different from one another, and
the first circuitry adjusts the access speed such that the access speed is higher in the sub-region which is closer to the processor.

12. The memory system according to claim 10 ,
wherein the plurality of sub-regions are used as a plurality of hierarchical cache memories, and
among the plurality of sub-regions, the sub-region with a higher access speed is used as a lower-order cache memory.

13. A memory system comprising:
a non-volatile memory of which access speed is electrically controlled;
first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory; and
second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
wherein the first circuitry is permitted to select a plurality of the first regions, and
when the first circuitry selects the plurality of first regions, the second circuitry adjusts the access speed of each of the plurality of first regions to be higher than the access speed of the second region.

14. The memory system according to claim 13 ,
wherein the first circuitry selects the plurality of first regions in association with different processors.

15. A memory system comprising:
a non-volatile memory of which access speed is electrically controlled;
first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory; and
second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
wherein the first circuitry selects the first region on the basis of at least one of a latency of a processor, an endurance of the non-volatile memory, a frequency of access, and an access history,
wherein the second circuitry adjusts a voltage in the first region to be higher than a voltage in the second region.

16. The memory system according to claim 15 ,
wherein, when the first region comprises a plurality of sub-regions each having different access speed, the second circuitry adjusts the voltage such that the voltage is higher as the access speed of the sub-region is higher.

17. The memory system according to claim 15 ,
wherein, when a processor accesses the second region and performs a process, an interrupt process is performed, and
when the processor performs the interrupt process, the first circuitry moves data, which is used in the process performed by the processor before the interrupt process is performed, from the second region to the first region.

18. The memory system according to claim 15 ,
wherein, when a processor accesses the first region and performs a process, an interrupt process is performed, and
when the processor performs the interrupt process, the first circuitry moves data, which is used in the process performed by the processor before the interrupt process is performed, from the first region to the second region.

19. The memory system according to claim 15 ,
wherein the non-volatile memory is a magnetoresistive random access memory (MRAM).

Assignees

• Toshiba Kk

Inventors

• Saida Daisuke
• Takeda Susumu
• Noguchi Hiroki
• Abe Kazuhiko

Classifications

• G06F2212/222

  Non-volatile memory · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title