Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture

Patent metadata

Field	Value
Publication number	US-9958932-B2
Application number	US-201414548912-A
Country	US
Kind code	B2
Filing date	Nov 20, 2014
Priority date	Nov 20, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

First claim

What is claimed is:

1. A processor apparatus comprising:
a plurality of processor cores, wherein:
the processor cores implement at least a portion of an instruction set architecture employed by the processor apparatus;
the instruction set architecture specifies a plurality of operand sizes for a first operand type;
a first processor core of the plurality of processor cores implements only a first operand size of the plurality of operand sizes, wherein a first instruction is executable by the first processor core in the event that the first instruction uses the first operand size and the first instruction is not executable by the first processor core in the event that the first instruction uses a different operand size of the plurality of operand sizes;
a second processor core of the plurality of processor cores implements the plurality of operand sizes, wherein the first instruction is executable by the second processor core with any of the plurality of operand sizes; and
at most one of the plurality of processor cores is active at a given point in time, except during a context switch between two of the plurality of processor cores; and

a processor power manager coupled to the plurality of processor cores, wherein the processor power manager is programmable with a plurality of processor states, wherein each of the plurality of processor states maps to one of the plurality of processor cores, and wherein the processor power manager is configured to:
detect that the processor power manager has been programmed to change a current processor state mapped to the second processor core to a requested processor state mapped to the first processor core during a time that code is being executed by the second processor core;
cause the change to the requested power state and a transfer of a processor context from the second processor core to the first processor core in response to being programmed to change from the current processor state to the requested processor state and further in response to detecting that the code uses only the first operand size, wherein the first processor core is configured to continue execution of the code responsive to the transfer; and
prevent the change to the requested power state and prevent the transfer to the first processor core and continue execution of the code the second processor core responsive to detecting that the code uses one or more operand sizes of the plurality of operand sizes that are different from the first operand size.

2. The processor apparatus as recited in claim 1 , wherein the processor power manager is configured to:
activate the second processor core and deactivate the first processor core responsive to the code being executed on the first processor core and the code using the one or more operand sizes.

3. The processor apparatus as recited in claim 1 , wherein:
the first processor core is configured to detect the use of the one or more operand sizes during execution of the code and to signal an exception in response to detecting the use; and
the exception indicates to the processor power manager that the code uses the one or more operand sizes.

4. The processor apparatus as recited in claim 3 , wherein the processor power manager is configured to cause the transfer of the processor context from the first processor core to the second processor core responsive to the exception.

5. The processor apparatus as recited in claim 4 , wherein the processor power manager comprises a non-transitory computer accessible storage medium storing a plurality of instructions executable by the processor apparatus.

6. The processor apparatus as recited in claim 3 , wherein:
the first processor core is configured to detect that a different feature of the instruction set architecture is not implemented by any core of the plurality of cores; and
the first processor core is configured to signal a different exception in response to detecting use of the different feature.

7. The processor apparatus as recited in claim 1 , wherein the processor power manager is configured to:
power on the second processor core; and
power down the first processor core responsive to transferring the processor context to the second processor core.

8. The processor apparatus as recited in claim 1 wherein the instruction set architecture further specifies a vector instruction set that is not implemented by the first processor core.

9. The processor apparatus as recited in claim 1 wherein the instruction set architecture further specifies a predicated vector instruction set that is not implemented by the first processor core.

10. The processor apparatus as recited in claim 1 wherein the first operand size is a largest operand size of the plurality of operand sizes.

11. A processor apparatus employing an instruction set architecture, the processor apparatus comprising:
a plurality of processor cores, wherein:
a first processor core of the plurality of processor cores implements a subset of the instruction set architecture;
a second processor core of the plurality of processor cores implements an entirety of the instruction set architecture;
the instruction set architecture specifies a plurality of operand sizes for a first operand type;
the subset implemented by the first processor core is the instructions that employ a first operand size of the plurality of operand sizes; and
at most one of the plurality of processor cores is active at a given point in time, except during a context switch between two of the plurality of processor cores; and

a processor power manager coupled to the plurality of processor cores, wherein:
the processor power manager is configured to activate the second processor core and deactivate the first processor core responsive to code that uses one or more operand sizes of the plurality of operand sizes that are different from the first operand size;
the processor power manager is programmable with a plurality of processor states, wherein each of the plurality of processor states maps to one of the plurality of processor cores;
the processor power manager is configured to detect that the processor power manager has been programmed to change a current processor state mapped to the second processor core to a requested processor state mapped to the first processor core during a time that code is being executed by the second processor core;
cause the change to the requested power state and a transfer of a processor context from the second processor core to the first processor core in response to being programmed to change from the current processor state to the requested processor state and further in response detecting that the code uses only the first operand size, wherein the first processor core is configured to continue execution of the code responsive to the transfer; and
the processor power manager is configured to prevent the change to the requested power state and prevent the transfer to the first processor core and continue execution of the code the second processor core responsive to the code using the one or more operand sizes.

12. The processor apparatus as recited in claim 11 wherein the first processor core is configured to detect the one or more operand sizes during execution of the code and indicate the detection to the processor power manager.

13. The processor apparatus as recited in claim 12 wherein the indication is an exception.

14. The processor apparatus as recited in claim 11 wherein the processor power manager is configured to cause the transfer of the processor context from the first processor to the second processor core to activate the second processo

Assignees

• Apple Inc

Inventors

• Williamson David J
• Williams Iii Gerard R
• Hardage Jr James N
• Russo Richard F

Classifications

• G06F9/5044

  considering hardware capabilities · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title