Method and apparatus for controlling an operating mode of a processing module

Patent metadata

Field	Value
Publication number	US-9958928-B2
Application number	US-201314899190-A
Country	US
Kind code	B2
Filing date	Jul 9, 2013
Priority date	Jul 9, 2013
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.

First claim

The invention claimed is:

1. A method of controlling an operating mode of at least one processing module; the method comprising:
receiving an indication of the execution of at least one background task by the at least one processing module;
aggregating an execution duration for the at least one background task on the at least one processing module;
determining whether the aggregated execution duration for the at least one background task exceeds a threshold duration within one of a plurality of repeated evaluation periods; and
if the aggregated execution duration for the at least one background task exceeds a threshold duration within one of the repeated evaluation periods:
switching a power mode for the at least one processing module to a lower power mode from a higher power mode when the at least one background task is allocated to the at least one processing module for execution thereon;
while the at least one processing module is in the lower power mode, switching the at least one processing module from the lower power mode to the higher power mode when a timing-critical task is allocated to the at least one processing module for execution thereon;
receiving a reset signal in response to an expiration of the one of the repeated evaluation periods; and
resetting the aggregated execution duration for the at least one background task in response to receiving the reset signal.

2. The method of claim 1 , wherein the indication of the execution of the at least one background task comprises at least one of:
a process identifier;
an instruction fetch address; and
an interrupt priority level.

3. The method of claim 1 , wherein the method comprises aggregating the execution duration for the at least one background task based at least partly on at least one of:
a clock cycle count value; and
a timing signal aggregator value.

4. The method of claim 1 , wherein the lower power mode for the at least one processing module comprises an inactive mode.

5. The method of claim 1 , wherein the method comprises configuring the higher power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task does not exceed the threshold duration.

6. The method of claim 1 , wherein the method comprises configuring the lower power mode for the at least one processing module by way of a WAIT control signal provided to a hardware power management component.

7. The method of claim 1 , wherein the method comprises configuring the lower power mode for the at least one processing module by way of a low-priority interrupt request.

8. Power mode control circuitry to control an operating mode of a processing module, the power mode control circuitry to:
receive an indication of the execution of at least one background task by the at least one processing module;
aggregate an execution duration for the at least one background task on the at least one processing module; and
determine whether the aggregated execution duration for the at least one background task exceeds a threshold duration within one of a plurality of repeated evaluation periods; and
if the aggregated execution duration for the at least one background task exceeds a threshold duration within one of the repeated evaluation periods:
switch a power mode for the at least one processing module to a lower power mode from a higher power mode when the at least one background task is allocated to the at least one processing module for execution thereon;
while the at least one processing module is in the lower power mode, switch the at least one processing module from the lower power mode to the higher power mode when a timing-critical task is allocated to the at least one processing module for execution thereon;
receive a reset signal in response to an expiration of the one of the repeated evaluation periods; and
reset the aggregated execution duration for the at least one background task in response to receiving the reset signal.

9. The power mode control circuitry of claim 8 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.

10. A signal processing device comprising at least one power mode control circuitry according to claim 8 .

11. The power mode control circuitry of claim 8 , wherein the indication of the execution of the at least one background task comprises at least one of:
a process identifier;
an instruction fetch address; and
an interrupt priority level.

12. The power mode control circuitry of claim 8 , wherein the aggregation of the execution duration for the at least one background task is based at least partly on at least one of:
a clock cycle count value; and
a timing signal aggregator value.

13. The power mode control circuitry of claim 8 , wherein the lower power mode for the at least one processing module comprises an inactive mode.

14. The power mode control circuitry of claim 8 , wherein the power mode control circuitry further to configure the higher power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task does not exceed the threshold duration.

15. The power mode control circuitry of claim 8 , wherein the power mode control circuitry further to configure the lower power mode for the at least one processing module by way of a WAIT control signal provided to a hardware power management component.

16. The power mode control circuitry of claim 8 , wherein the power mode control circuitry further to configure the lower power mode for the at least one processing module by way of a low-priority interrupt request.

17. A method of controlling an operating mode of a processing module, the method comprising:
receiving an indication of the execution of first and second background tasks by the processing module;
aggregating an execution duration for the first and second background tasks on the processing module;
determining whether the aggregated execution duration for the at least one background task exceeds a threshold duration within one of a plurality of repeated evaluation periods; and
if the aggregated execution duration for the first and second background tasks exceeds a threshold duration within one of the repeated evaluation periods:
switching a power mode for the at least one processing module to a lower power mode from a higher power mode when the first and second background tasks are allocated to the at least one processing module for execution thereon;
while the at least one processing module is in the lower power mode, switching the at least one processing module from the lower power mode to the higher power mode when a timing-critical task is allocated to the at least one processing module for execution thereon;
receiving a reset signal in response to an expiration of a timer of a first evaluation period of the one of the repeated evaluation periods; and
resetting the aggregated execution duration for the first and second background tasks in response to receiving the reset signal.

18. The method of claim 17 , wherein a second evaluation period of the one of the repeated evaluation periods begins after the reset signal is received.

Assignees

• Maiolani Mark
• Circello Joseph
• Marshall Ray
• Nxp Usa Inc

Inventors

• Maiolani Mark
• Circello Joseph
• Marshall Ray

Classifications

• G06F13/14 Primary

  Handling requests for interconnection or transfer · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• Y02B60/121

  Cross-Sectional Technologies · mapped topic

• G05B15/02

  electric · CPC title

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic