Implementation of related clocks

Patent metadata

Field	Value
Publication number	US-9954530-B2
Application number	US-201514599728-A
Country	US
Kind code	B2
Filing date	Jan 19, 2015
Priority date	Feb 27, 2013
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a plurality of configurable circuits for performing a plurality of operations, each operation defined by one of a plurality of different sets of configuration data, wherein each configurable circuit of the plurality of configurable circuits comprises:
a reconfiguration signal generator for generating a reconfiguration signal that includes data that corresponds to a reconfiguration state for selecting a set of the configuration data from the plurality of sets of configuration data, wherein the reconfiguration signal generator comprises a counter configured to update the reconfiguration signal.

2. The IC of claim 1 , wherein the counter is a reconfiguration counter that increments a count in response to receiving a count enable signal, wherein the count enable signal is modulated such that the configurable circuits perform the plurality of operations at a user specified data rate, and wherein the user specified data rate corresponds to a user defined clock.

3. The IC of claim 2 , wherein the plurality of operations is performed as part of a user design, where the user design is specified by using the user defined clock.

4. The IC of claim 2 , wherein the plurality of operations is for performing user defined operations that are defined by referencing the user defined clock.

5. The IC of claim 2 , wherein the reconfiguration counter operates on a base clock that is faster than the user defined clock.

6. The IC of claim 2 , wherein the count of the reconfiguration counter returns to an initial count when the reconfiguration state reaches a final reconfiguration state.

7. The IC of claim 1 , wherein the reconfiguration state loopers to an initial reconfiguration state after reaching a terminal count.

8. The IC of claim 1 , wherein each configurable circuit of the plurality of configurable circuits further comprises:
configurable logic; and
a context switcher that receives the reconfiguration signal from the reconfiguration signal generator and that uses the reconfiguration signal to load the selected set of the configuration data from the plurality of sets of configuration data to reconfigure the configurable logic.

9. An integrated circuit (IC) comprising:
a primary clock signal having a frequency;
a first set of reconfigurable circuits for implementing a user design, wherein the first set of reconfigurable circuits performs a first set of operations, and wherein the first set of operations is performed during a first sub-cycle of the primary clock signal; and
a second set of reconfigurable circuits for implementing the user design, wherein the second set of reconfigurable circuits performs a second set of operations, wherein the second set of operations is performed during a second sub-cycle of the primary clock signal that is different from the first sub-cycle, wherein the first and second sets of operations are each defined by a respective one of a plurality of different sets of configuration data, wherein each respective reconfigurable circuit in the first and second sets of reconfigurable circuits comprises:
a reconfiguration signal generator for generating a reconfiguration signal that includes data that corresponds to a reconfiguration state for the respective reconfigurable circuit; and
a context switcher that receives the reconfiguration signal from the reconfiguration signal generator and that configures the respective reconfigurable circuit with a selected set of configuration data from the plurality of sets of configuration data based on the data in the reconfiguration signal.

10. The IC of claim 9 , further comprising:
a third set of reconfigurable circuits for implementing the user design, wherein the third set of reconfigurable circuits performs a third set of operations, wherein the third set of operations is performed during a third sub-cycle of the primary clock signal that is different from the first and second sub-cycles.

11. The IC of claim 10 , further comprising:
a fourth set of reconfigurable circuits for implementing the user design, wherein the fourth set of reconfigurable circuits performs a fourth set of operations, wherein the fourth set of operations is performed during a fourth sub-cycle of the primary clock signal that is different from the first, second, and third sub-cycles.

12. The IC of claim 11 , wherein the first, second, third, and fourth sub-cycles occur sequentially and make up a single cycle of the primary clock signal.

13. The IC of claim 12 , wherein the first, second, third, and fourth sets of operations are each performed at a frequency that is at least four times higher than the frequency of the primary clock signal.

14. The IC of claim 9 , wherein the IC is reconfigured after each sub-cycle of the primary clock signal.

15. A method of operating a reconfigurable integrated circuit (IC), comprising:
with a plurality of configurable circuits, performing operations each of which is defined by a respective one of a plurality of different sets of configuration data;
with a reconfiguration signal generator, generating a reconfiguration signal that includes data that corresponds to a reconfiguration state, wherein generating the reconfiguration signal comprises incrementing a count of a counter circuit within the reconfiguration signal generator; and
selecting a set of the configuration data from the plurality of different sets of configuration data based on the reconfiguration state.

16. The method of claim 15 , wherein incrementing the count of the counter circuit within the reconfiguration signal generator comprises incrementing a count of a reconfiguration counter in response to receiving a count enable signal at the reconfiguration counter, the method further comprising:
modulating the count enable signal such that the configurable circuits perform the operations at a user specified data rate, wherein the user specified data rate corresponds to a user defined clock signal.

17. The method of claim 16 , wherein the operations is performed as part of a user design, the method further comprising:
specifying the user design by using the user defined clock signal.

18. The method of claim 16 , wherein performing the operations further comprises:
performing user defined operations that are defined by referencing the user defined clock signal to align the reconfiguration state with the user defined clock signal.

19. The method of claim 16 , further comprising:
operating the reconfiguration counter using a base clock signal that is faster than the user defined clock signal.

20. The method of claim 16 , further comprising:
returning the count of the reconfiguration counter to an initial count value when the reconfiguration state reaches a final reconfiguration state.

21. The method of claim 16 , further comprising:
loopering the reconfiguration state to an initial reconfiguration state after reaching a terminal count.

22. The method of claim 15 , further comprising:
with a context switcher, receiving the reconfiguration signal from the reconfiguration signal generator; and
with the context switcher, using the reconfiguration signal to configure one of the plurality of configurable circuits with the selected set of configuration data.

Assignees

• Altera Corp

Inventors

• Ebeling Christopher D
• Wrighton Michael Glenn
• Caldwell Andrew
• Townley Kent

Classifications

• H03K19/173 Primary

  using elementary logic circuits as components · CPC title