Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9720879-B2
Application number	US-97373010-A
Country	US
Kind code	B2
Filing date	Dec 20, 2010
Priority date	Jan 27, 2010
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

First claim

What is claimed is:

1. A reconfigurable circuit comprising:
a plurality of processing elements; and
an input/output data interface unit implemented as a first portion of said reconfigurable circuit, said input/output data interface unit configured to hold operation input data which is input to said plurality of processing elements and operation output data which is output from said plurality of processing elements, and configured to control connections of said plurality of processing elements for each context of a plurality of contexts,
wherein said input/output data interface unit comprises:
a plurality of ports;
a plurality of multiplexers, wherein each multiplexer is coupled to a corresponding port of the plurality of ports; and
a matrix of registers having n+1 rows and m+1 columns of registers (m and n each being integers greater than 0) configured to be connected to said plurality of multiplexers such that the only registers connected to each multiplexer of the plurality of multiplexers is a corresponding row of m+1 registers, wherein the registers are configured to be allocated to a particular context of the plurality of contexts based on particular configuration data associated with that particular context, wherein the particular configuration data specifies particular register input bank selection information and particular register output bank selection information for that particular context, and wherein the particular register input bank selection information is distinct from the particular register output bank selection information.

2. The reconfigurable circuit according to claim 1 , further comprising:
a data processing unit implemented as a second portion of said reconfigurable circuit, said data processing unit including said plurality of processing elements;
a data network unit implemented as a third portion of said reconfigurable circuit, said data network unit configured to control the connection of said plurality of ports and said plurality of processing elements; and
a register control unit implemented as a fourth portion of said reconfigurable circuit, said register control unit configured to control the registers of said input/output data interface unit.

3. The reconfigurable circuit according to claim 2 , wherein configuration data is held for each said context of the plurality of contexts, wherein the configuration data for each said context includes register input bank selection information of the ports configured to indicate to which banks of registers of the ports to write the operation output data from said data processing unit; and said register control unit is configured to generate a reconfigurable circuit write enable signal for a register of a target bank for a write operation of said ports based on said register input bank selection information of the ports.

4. The reconfigurable circuit according to claim 3 , wherein the configuration data for each said context includes register output bank selection information of the ports configured to indicate from which banks of registers of the ports to output the operation input data to said data processing unit; and
said input/output data interface unit further comprises a first selector configured to select a target bank for output of data from the ports based on the register output bank selection information of the ports.

5. The reconfigurable circuit according to claim 4 , further comprising a configuration data holding unit implemented as a fifth portion of said reconfigurable circuit, said configuration data holding unit comprising:
a memory configured to store the configuration data of each of said contexts;
a programmable counter configured to designate an address of said memory; and
a configuration data selection circuit configured to select data held at an address designated by said programmable counter and to output various types of configuration data including said register output bank selection information and said register input bank selection information of the ports.

6. The reconfigurable circuit according to claim 3 , wherein said register control unit further comprises:
a first logic circuit configured to receive said reconfigurable circuit write enable signal and an external circuit write enable signal and to assert a register write enable signal in a corresponding register when one of the enable signals is asserted; and
an external/internal write data selection signal generation circuit configured to select said operation output data when said reconfigurable circuit write enable signal is asserted and to select operation input data from a particular external circuit when said external circuit write enable signal is asserted.

7. The reconfigurable circuit according to claim 6 wherein said input/output data interface unit further comprises a second selector configured to select data to be held at said matrix of registers from said operation input data or said operation output data based on said external/internal write data selection signal.

8. The reconfigurable circuit according to claim 6 , wherein:
said register control unit further comprises an output data selection signal generation circuit configured to generate an output data selection signal for selecting a register output corresponding to an address value from address information indicating a target of registers from said external circuit; and
said input/output data interface unit further comprises a third selector configured to select register output data based on said output data selection signal and to output said register output data to the external circuit.

9. The reconfigurable circuit according to claim 6 , wherein said register control unit further comprises:
an external circuit/reconfigurable circuit simultaneous write detection unit implemented as a sixth portion of said reconfigurable circuit, said external circuit/reconfigurable circuit simultaneous write detection unit configured to detect when said reconfigurable circuit write enable signal and said external circuit write enable signal are simultaneously asserted; and
a priority judgment unit implemented as a seventh portion of said reconfigurable circuit, said priority judgment unit configured to judge priority based on an external circuit/reconfigurable circuit write priority signal defining which write operation from said particular external circuit to give priority to when said reconfigurable circuit write enable signal and said external circuit write enable signal are simultaneously asserted.

10. The reconfigurable circuit according to claim 9 , wherein said external circuit/reconfigurable circuit simultaneous write detection unit detects when said reconfigurable circuit write enable signal and said external circuit write enable signal are simultaneously asserted and outputs a simultaneous write detection signal as error information to said particular external circuit.

11. The reconfigurable circuit according to claim 1 , wherein said reconfigurable circuit is a dynamic reconfigurable circuit configured to dynamically change its circuit configuration along with time based on a context from said plurality of contexts.

12. A semiconductor integrated circuit comprising:
a reconfigurable circuit; and
an external circuit,
wherein said reconfigurable circuit comprises:
a plurality of processing elements; and
an input/output data interface unit implemented as a first portion of said reconfigurable circuit, said input/output data interface unit configured to hold operation input data which is input to said plurality of processing elements and operation output data which is output from said plurality of processing elements, and configured to c

Assignees

• Sutou Shinichi
• Kasama Ichiro
• Sato Kyoji
• Hanai Takashi
• Katou Kiyomitsu
• Kubota Takahiro
• Sahoda Junji
• Cypress Semiconductor Corp

Inventors

• Sutou Shinichi
• Kasama Ichiro
• Sato Kyoji
• Hanai Takashi
• Katou Kiyomitsu
• Kubota Takahiro
• Sahoda Junji

Classifications

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title