Integrated circuit comprising fractional clock multiplication circuitry

Patent metadata

Field	Value
Publication number	US-9954489-B2
Application number	US-201715632045-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Nov 28, 2011
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a master clock generator comprising a ring oscillator, wherein the master clock generator outputs a first clock signal, and wherein an adjustment is made to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal; and
a set of fractional clock multipliers, wherein each fractional clock multiplier comprises an injection-locked oscillator (ILO), wherein an adjustment is made to a loop delay of each ILO based on the adjustment that is made to the loop delay of the ring oscillator, and wherein each ILO generates a second clock signal based on the first clock signal.

2. The integrated circuit of claim 1 , wherein the integrated circuit is a processor, and wherein the second clock signal is provided to one of: an arithmetic logic unit, a floating point unit, or a memory load/store unit.

3. The integrated circuit of claim 1 , wherein each fractional clock multiplier comprises:
circuitry to generate an injection signal based on the first clock signal;
circuitry to periodically select a different injection location in the ILO; and
circuitry to inject the injection signal into the selected injection location in the ILO.

4. The integrated circuit of claim 3 , wherein the circuitry to periodically select the different injection location comprises:
a plurality of gates, wherein an output of each gate is coupled to an injection location in the ILO; and
circuitry to generate a plurality of gating signals, wherein each gating signal is provided to a corresponding gate in the plurality of gates.

5. The integrated circuit of claim 1 , wherein each fractional clock multiplier comprises:
circuitry to generate a plurality of injection signals based on the first clock signal;
circuitry to periodically select a different injection signal from the plurality of injection signals; and
circuitry to inject the selected injection signal into the ILO.

6. The integrated circuit of claim 5 , wherein the circuitry to periodically select the different injection signal comprises:
a multiplexer to select an injection signal from the plurality of injection signals based on a select signal; and
circuitry to periodically change the select signal.

7. The integrated circuit of claim 1 , wherein each fractional clock multiplier comprises:
circuitry to generate a plurality of injection signals based on the first clock signal;
circuitry to periodically select a different injection signal from the plurality of injection signals;
circuitry to periodically select a different injection location in the ILO; and
circuitry to inject the selected injection signal into the selected injection location in the ILO.

8. A method, comprising:
generating a first clock signal by using a master clock generator, wherein the master clock generator comprises a ring oscillator;
making adjustments to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal;
generating a second clock signal by using a fractional clock multiplier, wherein the fractional clock multiplier generates the second clock signal based on the first clock signal by using an injection-locked oscillator (ILO); and
making adjustments to a loop delay of the ILO based on the adjustment that is made to the loop delay of the ring oscillator.

9. The method of claim 8 , comprising providing the second clock signal to one of: an arithmetic logic unit, a floating point unit, or a memory load/store unit.

10. The method of claim 8 , wherein said generating the second clock signal comprises:
generating an injection signal based on the first clock signal;
periodically selecting a different injection location in the ILO; and
injecting the injection signal into the selected injection location in the ILO.

11. The method of claim 10 , wherein said periodically selecting the different injection location in the ILO comprises:
generating a plurality of gating signals; and
providing each gating signal in the plurality of gating signals to a corresponding gate in a plurality of gates, wherein an output of each gate in the plurality of gates is coupled to an injection location in the ILO.

12. The method of claim 8 , wherein said generating the second clock signal comprises:
generating a plurality of injection signals based on the first clock signal;
periodically selecting a different injection signal from the plurality of injection signals; and
injecting the selected injection signal into the ILO.

13. The method of claim 12 , wherein said periodically selecting the different injection signal from the plurality of injection signals comprises:
using a multiplexer to select an injection signal from the plurality of injection signals based on a select signal; and
periodically changing the select signal.

14. The method of claim 8 , wherein said generating the second clock signal comprises:
generating a plurality of injection signals based on the first clock signal;
periodically selecting a different injection signal from the plurality of injection signals;
periodically selecting a different injection location in the ILO; and
injecting the selected injection signal into the selected injection location in the ILO.

15. An integrated circuit, comprising:
a first clock domain comprising circuitry that is clocked by a first clock signal;
a master clock generator comprising a ring oscillator, wherein the master clock generator outputs the first clock signal, and wherein an adjustment is made to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal;
a fractional clock multiplier comprising an injection-locked oscillator (ILO), wherein an adjustment is made to a loop delay of the ILO based on the adjustment that is made to the loop delay of the ring oscillator, and wherein the ILO generates a second clock signal based on the first clock signal; and
a second clock domain comprising circuitry that is clocked by the second clock signal.

16. The integrated circuit of claim 15 , wherein the integrated circuit is a processor, wherein the first clock domain comprises front-end processing circuitry, and wherein the second clock domain comprises one of: an arithmetic logic unit, a floating point unit, or a memory load/store unit.

17. The integrated circuit of claim 15 , wherein the fractional clock multiplier comprises:
circuitry to generate an injection signal based on the first clock signal;
circuitry to periodically select a different injection location in the ILO; and
circuitry to inject the injection signal into the selected injection location in the ILO.

18. The integrated circuit of claim 17 , wherein the circuitry to periodically select the different injection location comprises:
a plurality of gates, wherein an output of each gate is coupled to an injection location in the ILO; and
circuitry to generate a plurality of gating signals, wherein each gating signal is provided to a corresponding gate in the plurality of gates.

19. The integrated circuit of claim 15 , wherein the fractional clock multiplier comprises:
circuitry to generate a plurality of injection signals based on the first clock signal;
circuitry to periodically select a different injection signal from the plurality of injection signals; and
circuitry to inj

Assignees

• Rambus Inc

Inventors

• Hossain Masum
• Aryanfar Farshid
• Hekmat Mohammad
• Navid Reza

Classifications

• H03B19/00 Primary

  Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source (transference of modulation from one carrier to another H03D7/00) · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title