Systems and methods for generating injection-locked, frequency-multiplied output signals

Patent metadata

Field	Value
Publication number	US-9564880-B2
Application number	US-201414581337-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).

First claim

What is claimed is:

1. A circuit system comprising a frequency-multiplication circuit, the frequency-multiplication circuit comprising:
a ring of a number (N) of serially connected delay-buffer elements that each provide an equal time delay (D), at least some of the delay-buffer elements having at least one pulse-locking injection port, the pulse-locking injection port being an edge driven pulse-locking injection port, the ring having a ring output port; and
an injection-pulse-generation circuit comprising:
a clock input port configured to receive a clock signal having a clock-signal frequency (F CLK ) and a corresponding clock-signal period (T CLK );
a pulse-selection input port configured to receive pulse-selection control signals;
a plurality of injection-pulse output ports connected to respective pulse-locking injection ports of the delay-buffer elements; and
balanced-delay selection-logic circuitry connected to the clock input port, the pulse-selection input port, and the injection-pulse output ports,
wherein the injection-pulse generation circuit is configured to:
generate balanced-delay injection-pulse signals by applying the balanced-delay selection-logic circuitry to the clock signal according to the pulse-selection control signals by generating one or more falling-edge injection-pulse signals responsive to one or more respective falling edges of the clock signal; and
provide an injection-locked, frequency-multiplied ring output signal at the ring output port by transmitting the generated balanced-delay injection-pulse signals via the injection-pulse output ports to the respectively connected pulse-locking injection ports, the ring output signal having an output-signal frequency (F OUT ) that equals the reciprocal of (N*D) and that bears the same proportional relationship to F CLK that T CLK bears to (N*D).

2. The circuit system of claim 1 , further comprising a clock-generation circuit configured to transmit the clock signal to the injection-pulse-generation circuit.

3. The circuit system of claim 1 , further comprising a controller configured to transmit the pulse-selection control signals to the injection-pulse-generation circuit.

4. The circuit system of claim 1 , wherein N is an even number.

5. The circuit system of claim 4 , wherein N equals 4.

6. The circuit system of claim 4 , wherein N equals 8.

7. The circuit system of claim 4 , wherein N equals 16.

8. The circuit system of claim 1 , wherein at least one of the delay-buffer elements comprises a pair of inverter circuits.

9. A circuit system comprising a frequency-multiplication circuit, the frequency-multiplication circuit comprising:
a ring of a number (N) of serially connected delay-buffer elements that each provide an equal time delay (D), at least some of the delay-buffer elements having at least one pulse-locking injection port, the pulse-locking injection port being an edge driven pulse-locking injection port, the ring having a ring output port; and
an injection-pulse-generation circuit comprising:
a clock input port configured to receive a clock signal having a clock-signal frequency (F CLK ) and a corresponding clock-signal period (T CLK );
a pulse-selection input port configured to receive pulse-selection control signals;
a plurality of injection-pulse output ports connected to respective pulse-locking injection ports of the delay-buffer elements, wherein each of the delay-buffer elements has at least one pulse-locking injection port connected to a respective one of the injection-pulse output ports of the injection-pulse generation circuit, wherein each of those pulse-locking injection ports comprises a rising-edge pulse-locking injection port;
balanced-delay selection-logic circuitry connected to the clock input port, the pulse-selection input port, and the injection-pulse output ports,
wherein the injection-pulse generation circuit is configured to:
generate balanced-delay injection-pulse signals by applying the balanced-delay selection-logic circuitry to the clock signal according to the pulse-selection control, provide an injection-locked, frequency-multiplied ring output signal at the ring output port by transmitting the generated balanced-delay injection-pulse signals via the injection-pulse output ports to the respectively connected pulse-locking injection ports, the ring output signal having an output-signal frequency (F OUT ) that equals the reciprocal of (N*D) and that bears the same proportional relationship to F CLK that T CLK bears to (N*D).

10. The circuit system of claim 9 , wherein each of those pulse-locking injection ports further comprises a falling-edge pulse-locking injection port.

11. A circuit system comprising a frequency-multiplication circuit, the frequency-multiplication circuit comprising:
a ring of a number (N) of serially connected delay-buffer elements that each provide an equal time delay (D), at least some of the delay-buffer elements having at least one pulse-locking injection port, the pulse-locking injection port being an edge driven pulse-locking injection port, the ring having a ring output port; and
an injection-pulse-generation circuit comprising:
a clock input port configured to receive a clock signal having a clock-signal frequency (F CLK ) and a corresponding clock-signal period (T CLK );
a pulse-selection input port configured to receive pulse-selection control signals;
a plurality of injection-pulse output ports connected to respective pulse-locking injection ports of the delay-buffer elements; and
balanced-delay selection-logic circuitry connected to the clock input port, the pulse-selection input port, and the injection-pulse output ports,
wherein the injection-pulse generation circuit is configured to:
generate balanced-delay injection-pulse signals by applying the balanced-delay selection-logic circuitry to the clock signal according to the pulse-selection control signals by generating one or more rising-edge injection-pulse signals responsive to one or more respective rising edges of the clock signal; and
provide an injection-locked, frequency-multiplied ring output signal at the ring output port by transmitting the generated balanced-delay injection-pulse signals via the injection-pulse output ports to the respectively connected pulse-locking injection ports, the ring output signal having an output-signal frequency (F OUT ) that equals the reciprocal of (N*D) and that bears the same proportional relationship to F CLK that T CLK bears to (N*D).

12. The circuit system of claim 11 , wherein generating the balanced-delay injection-pulse signals by applying the balanced-delay selection-logic circuitry to the clock signal according to the pulse-selection control signals further comprises generating one or more falling-edge injection-pulse signals responsive to one or more respective falling edges of the clock signal.

13. A circuit system comprising a frequency-multiplication circuit, the frequency-multiplication circuit comprising:
a ring of a number (N) of serially connected delay-buffer elements that each provide an equal time delay (D), at least some of the delay-buffer elements having at least one pulse-locking injection port, the pulse-locking injection port being an edge driven pulse-locking injection port, the ring having a ring output port; and
an injection-pulse-generation circuit comprising:
a clock input port configured to receive a clock signal having a clock-signal frequency (F CLK ) and a corresponding clock-signal period (T CLK );
a pulse-selection input port configured to receive pulse-selection control signals;
a plurality of injection-pulse output ports connected to respective pulse

Assignees

• Motorola Solutions Inc

Inventors

• Stengel Robert E
• Cafaro Nicholas G

Classifications

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03K3/0315 Primary

  Ring oscillators · CPC title