Thin film transistor and manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-9954070-B2
Application number	US-201514913581-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Mar 25, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A thin film transistor, a manufacturing method thereof, and a display device are provided. The thin film transistor includes a gate electrode ( 21 ), an active layer ( 23 ), a source electrode ( 241 ) and a drain electrode ( 242 ). The source electrode ( 241 ) and the drain electrode ( 242 ) are formed of at least two materials, the forming materials of the source electrode ( 241 ) and the drain electrode ( 242 ) can create a cell reaction in a corresponding etching solution so as to be etched, and material of the active layer ( 23 ) is not corroded by the etching solution. With the thin film transistor and manufacturing method thereof according to embodiments of the invention, a problem that an active layer is liable to be corroded in an etching procedure of a source electrode and a drain electrode can be solved, and thus the thin film transistor device can be manufactured by using a back channel etch process. Consequently, the process number for manufacture of the thin film transistor is decreased, and the manufacturing cost is saved.

First claim

The invention claimed is:

1. A manufacturing method of a thin film transistor, comprising the following steps:
providing a base substrate;
forming a gate electrode and a gate insulating layer;
forming an active layer, a source electrode, and a drain electrode, includes:
forming a first material layer and a second material layer, the second material layer having pinholes therein, the pinholes allowing an etching solution subsequently adopted to get through the second material layer; and
etching the first material layer and the second material layer by a cell reaction in the etching solution so as to form a source electrode and a drain electrode, wherein, the etching solution passes through the pinholes of the second material layer, and the first material layer and the second material layer simultaneously encounter the etching solution; wherein, in the cell reaction, one of the first material layer and the second material layer is oxidized and the other one of the first material layer and the second material layer is reduced, and a material of the active layer is not corroded by the etching solution.

2. The manufacturing method claimed as claim 1 , wherein, the source electrode and the drain electrode are a composite conductive film layer formed of a part of the first material layer and a part of the second material layer.

3. The manufacturing method claimed as claim 2 , wherein,
the pinholes in the second material layer is formed by way of sputtering.

4. The manufacturing method claimed as claim 1 , wherein, forming the active layer, the source electrode and the drain electrode includes:
depositing a compound semiconductor thin film and the composite conductive film layer on the gate insulating layer; and
patterning the compound semiconductor thin film and the first material layer and the second material layer with a double-tone masking process, so as to obtain a compound semiconductor active layer and the source electrode, the drain electrode.

5. The manufacturing method claimed as claim 1 , wherein, the first material layer is aluminum layer and the second material layer is indium tin oxide layer; and the etching solution is an alkaline solution.

6. The manufacturing method claimed as claim 1 , after forming the first material layer and the second material layer, and before simultaneously etching the first material layer and the second material layer by a cell reaction in a corresponding etching solution, further comprising:
forming a metal layer on the first material layer and the second material layer; and
patterning the metal layer with an etching process, so that the metal layer in a region corresponding to the source electrode and the drain electrode is retained.

7. The manufacturing method claimed as claim 4 , wherein, a material of the compound semiconductor thin film includes one or more selected from the group consisting of indium gallium zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, zinc tin oxide, aluminum zinc tin oxide, aluminum zinc oxide, gallium zinc oxide, cadmium sulfide, cadmium selenide, cadmium telluride, gallium nitride, gallium phosphide, gallium arsenide and molybdenum sulfide.

8. The manufacturing method claimed as claim 6 , wherein, a material of the metal layer includes at least one of metal molybdenum and metal titanium.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Longyan
• Li Yongqian
• Cao Kun
• Li Quanhu
• Yin Jingwen
• Zhang Baoxia
• Gai Cuili
• Wu Zhongyuan
• Wang Gang

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L29/45 Primary

  Electricity · mapped topic